Hitachi Energy Ltd

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Abb Power Grids Switzerland Ag

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Hitachi Energy Switzerland Ag

Audi Ag

Marco Bellini

Florin Udrea

Lars Knoll

Jan Vobecky

Umamaheswara Vemulapati

Friedhelm Bauer

Gianpaolo Romano

Munaf Rahimo

Iulian Nistor

Maxi Andenna

Renato Minamisawa

Jürgen Schuderer

Stephan Wirths

Paul Commin

Andrei Mihaila

Lukas Kranz

Wolfgang Amadeus Vitale

Elizabeth Buitrago

Nazareno Donato

A power semiconductor device and method for production thereof is specified involving an electrode, a base layer of a first conductivity type provided on the electrode, at least one contact layer provided on the base layer, a gate contact provided on the base layer and on the at least one contact layer, an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type within the base layer, wherein the at least one zone is constructed and arranged to shift away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

Power semiconductor device and a method for producing a power semiconductor device

A power semiconductor device () comprising a semiconductor body () extending in a vertical direction between a first main surface () and a second main surface (), a trench () extending from the first main surface () into the semiconductor body () in the vertical direction, and an insulated trench gate electrode () that is formed on the first main surface () and extends into the trench () is specified, wherein the trench () is subdivided along a main extension direction of the trench () in a plurality of segments () and the insulated trench gate electrode () continuously extends over the plurality of segments ().

Power semiconductor device with an insulated trench gate electrode

A silicon carbide (SiC) planar transistor device includes a SiC semiconductor substrate of a first charge type, a SiC epitaxial layer of the first charge type formed at a top surface of the SiC semiconductor substrate, a source structure of the first charge type formed at a top surface of the SiC epitaxial layer, a drain structure of the first charge type formed at a bottom surface of the SiC semiconductor substrate, a gate structure comprising a gate runner and a gate dielectric that covers at least part of the source structure and the gate runner, and a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure. The channel can be formed by performing a plurality of implantation steps so that the channel region comprises a first region and a second region.

Planar SiC MOSFET with retrograde implanted channel

A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, a n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.

Silicon carbide transistor device

A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region.

Silicon carbide power device with MOS structure and stressor

A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

Power semiconductor module

A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

Silicon carbide superjunction power semiconductor device and method for manufacturing the same

In a power semiconductor device of the application a total number n of floating field rings (_to_) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation dbetween an i-th floating field ring and a directly adjacent (i&#x2212;1)-th floating field ring, when counting the floating field rings (_to_) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: d=d+&#x3a3;&#x394;for i=2 to n, wherein dis a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: &#x394;&#x2212;0.05&#xb7;&#x394;&#x3c;&#x394;&#x3c;&#x394;+0.05&#xb7;&#x394;for j=1 to I&#x2212;2, 2&#xb7;&#x394;&#x3c;|&#x394;|&#x3c;10&#xb7;&#x394;. for j=I&#x2212;1, 0.95&#xb7;&#x394;&#x3c;&#x394;&#x3c;1.05&#xb7;&#x394;for j=I to n&#x2212;1, &#x394;&#x3e;0.1 &#x3bc;m, and &#x2212;&#x394;/2&#x3c;&#x394;&#x3c;&#x394;/2, wherein I is an integer, for which 3&#x2264;l&#x2264;n/2.

Power semiconductor device with floating field ring termination

A thyristor is disclosed with a plurality of emitter shorts at points in the cathode region. The points define a Delaunay triangulation with a plurality of triangles. For a first subset of triangles a coefficient of variation of the values qwith l&#x2208;Sis smaller than 0.1, and/or an absolute value of a skewedness of the geometric quantities qwith l&#x2208;Sis smaller than 5, and/or a Kurtosis of the geometric quantities qwith l&#x2208;Sis smaller than 20. For a second subset of triangles, a quotient of a standard deviation of the quantities qwith m&#x2208;Sand a mean squared value of the geometric quantity qwith l&#x2208;Sis less than 1, and/or a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than 1.0&#xd7;10.

Phase control thyristor

There is provided a thyristor having emitter shorts, wherein in an orthogonal projection onto a plane parallel to a first main side, a contact area covered by an electrical contact of a first electrode layer with a first emitter layer and the emitter shorts includes areas in the shape of lanes, in which an area coverage of the emitter shorts is less than the area coverage of emitter shorts in the remaining area of the contact area, wherein the area coverage of the emitter shorts in a specific area is the area covered by the emitter shorts in that specific area relative to the specific area. The thyristor of the invention exhibits a fast turn-on process even without complicated amplifying gate structure.

Thyristor with improved plasma spreading

An insulated gate bipolar device is disclosed which can include layers of different conductivity types between an emitter electrode on an emitter side and a collector electrode on a collector side in the following order: a source region of a first conductivity type, a base layer of a second conductivity type, which contacts the emitter electrode in a contact area, an enhancement layer of the first conductivity type, a floating compensation layer of the second conductivity type having a compensation layer thickness t, a drift layer of the first conductivity type having lower doping concentration than the enhancement layer and a collector layer of the second conductivity type.

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Schlieren, Switzerland

Marco Bellini