Freescale Semiconductor,inc.

Marc J Olivares

Kevin D Lucas

Chi-Min Yuan

Kirk J Strozewski

A method ( ) for correcting lithography error includes generating ( ) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize ( ) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern ( ) has isolated features ( ) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern ( ) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.

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New Braunfels, TX, United States of America

Marc J Olivares