National Yang Ming Chiao Tung University

Faraday Technology Corporation

Mao-Chih Hsia

Wei Hwang

Chia-Cheng Chen

Hao-I Yang

Ching-Te Chuang

Wei-Chiang Shih

Shyh-Jye Jou

Ming-Hsien Tu

Chien-Yu Lu

Yung-Wei Lin

A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.

Low power static random access memory

A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.

Static random access memory with data controlled power supply

Growing community of inventors

Kaohsiung, Taiwan

Mao-Chih Hsia