Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Globalfoundries U.S. Inc.

Marvell International Limited

Marvell Asia Pte., Ltd.

Manjunatha Govinda Prabhu

Mahadeva Iyer Natarajan

Chien-Hsin Lee

David C Pritchard

Heng Yang

Hongru Ren

Neha Nayyar

Anil Kumar

Xiangxiang Lu

Salvatore Cimino

Da-Wei Lai

Elizabeth Strehlow

Kai Sun

Lixia Lei

Tsung-Che Tsai

Jagar Singh

George Jonathan Kluth

Anurag Mittal

Vikrant Kumar Chauhan

Wei Gao

Vaddagere Nagaraju Vasantha Kumar

Shan Ryan

Heng Lan Lau

Yi Shan

Shawn Walsh

Ryan Shan

Andy C Wei

Alain F Loiseau

Mahbub Rashed

Ryan W Sporer

William McMahon

Suresh Uppal

Zhixing Zhao

Sushama Davar

Shafiullah Syed

Ruchil Kumar Jain

A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

Planar transistor device comprising at least one layer of a two-dimensional (2D) material

A semiconductor device comprising an active region, and a gate having side portions and a middle portion, whereby the middle portion is arranged between the side portions. The side portions and the middle portion of the gate may be arranged over the active region. The middle portion may be horizontally wider than the side portions. A first gate contact may be arranged over the middle portion.

Semiconductor device having a gate contact over an active region

An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.

Well tap for an integrated circuit product and methods of forming such a well tap

Planar transistor device comprising at least one layer of a two-dimensional (2D) material and methods for making such transistor devices

The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Fully depleted devices with slots in active regions

One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.

Vertical transistor device comprising a two-dimensional (2D) material positioned in a channel region of the device and methods of making such vertical transistor devices

One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

Vertical transistor device with source/drain regions comprising a twi-dimensional (2D) material and methods of making such vertical transistor devices

A method includes accessing, from a memory, a schematic diagram of a circuit that depicts components of the circuit and, connected to one or more of the components, single-pin imaginary devices associated with group properties of the components. The method further includes automatically generating a design layout for the circuit based on the schematic diagram. The design layout comprises shapes representing the components and, on each shape representing a specific component that is connected to a single-pin imaginary device, a specific group label corresponding to a specific group property of the specific component. Placement of the shapes within the design layout is group label dependent. Accessing of the schematic diagram and the automatically generating of the design layout are performed by a layout generator tool executed by a processor of a computer-aided design system.

Integrated circuit methods using single-pin imaginary devices

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

Electrostatic discharge protection device

Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

Methods, apparatus, and system for metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic discharge (ESD) protection

High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Transistors patterned with electrostatic discharge protection and methods of fabrication

In the disclosed design systems and methods, a schematic diagram includes nets and, connected to at least some nets, single-pin first and second imaginary devices. On any given net, a first imaginary device is associated with a tracking group property of the net (where nets in the same tracking group are in-phase) and a second imaginary device is associated with a voltage property of the net. A design layout generated based on the schematic diagram includes: net shapes representing the nets and, on net shapes that represent nets connected to the imaginary devices, tracking group and voltage labels corresponding to the tracking group and voltage properties. Net shape placement within the design layout and design rule checking are performed according to design rules that dictate placing net shapes with the same tracking group label together and further dictate minimum allowable spacing requirements depending upon the tracking group and voltage labels.

Integrated circuit (IC) design systems and methods using single-pin imaginary devices

One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.

Auxiliary gate antenna diodes

Devices with slotted active regions

Integrated circuits with electrostatic discharge (ESD) protection and methods of providing ESD protection in an integrated circuit are provided. An ESD protection circuit the ESD protection circuit may incorporate a transistor, such as a MOSFET, and a voltage limiter coupled to a gate of the transistor. The voltage limiter may be configured such that with an ESD disturbance on the voltage supply rail, Vdd, a gate voltage of the transistor of the ESD protection circuit is held below the supply voltage (Vdd) inducing base current, Isub, within the transistor to effectively shunt a current arising from the ESD event from the voltage supply rail Vdd to the voltage supply rail Vss.

Integrated circuit electrostatic discharge protection

Growing community of inventors

Clifton Park, NY, United States of America

Manjunatha Govinda Prabhu