Synopsys, Inc.

Qualcomm Incorporated

Vmware, Inc.

Stmicroelectronics Gmbh

Manish Jain

Subha S Chowdhury

Sridhar Seshadri

Ashutosh Vinod Agrawal

Alberto Rico Alvarino

Alexei Yurievitch Gorokhov

Umesh Phuyal

Hari Sankar

Amir Farajidana

Farrokh Abrishamkar

Mani Kancherla

Roberto Alini

Keith William Saints

Wenshu Zhang

Nitin Pant

Timothy Paul Pals

Vaishakh Rao

Awlok Singh Josan

Jae Won Yoo

Aditya Dua

Omesh Kumar Handa

Badri P Gopalan

Parastoo Kheirkhah

Yogesh Pandey

Anoop Ramakrishna

Manav Lnu

Honey Kakkar

Farrukh Rashid

Parees Kambli

Venkata Pavan Kumar Bhargav Medepally

Kiran Singh Matharu

Manini Shah

Vijay Anand Sankar

Manu Krishnan Kavunkal

Abhishek Kumar

A method for wireless communication by a network node includes transmitting a first group of frames comprising a group of normal slots and one or more first special slots. The method also includes reconfiguring one or more second special slots within a second group of frames scheduled after the first group of frames based on a block error rate (BLER) associated with the group of normal slots failing to satisfy a BLER condition. The method further includes transmitting the second group of frames based on reconfiguring the one or more second special slots within the second group of frames.

Throughput improvement for radio frames containing time division duplex (TDD) special slots or TDD/frequency division duplex (FDD) rate-matched slots

Some embodiments of the invention provide a novel method for performing firewall operations on a computer. The method of some embodiments instantiates first and second firewall processes on the computer. These two processes are two separate processes, which in some embodiments have separate memory allocations in the memory system of the computer. The method uses the first firewall process to examine a data message to determine whether an encryption based firewall policy (e.g., a TLS-based firewall policy) has to be enforced on the data message. Based on a determination that the encryption-based firewall policy has to be enforced on the data message, the method provides metadata, which is produced by the first firewall process in its examination of the data message, to the second firewall process. The second firewall process then uses the provided metadata to perform an encryption-based firewall operation based on the encryption-based firewall policy. In some embodiments, the data message is encrypted, the first firewall process cannot decrypt the data message, and the second firewall process performs a decryption operation (e.g., a TLS-based decryption operation) to decrypt the data message.

Performing firewall operations by sharing metadata between firewall processes

To reduce power consumption, a user equipment (UE) may trigger a microsleep in a subframe when a physical downlink control channel (PDCCH) does not include a downlink grant. However, because the microsleep depends on the PDCCH not including a downlink grant, the UE cannot trigger the microsleep until after the PDCCH is decoded. Accordingly, in some aspects, a UE may enable an aggressive extra microsleep in which a microsleep duration may be increased by reducing a PDCCH decode time. For example, a UE may use a stale channel estimate and noise estimate from a previous subframe to perform PDCCH demapping when conditions related to a PDCCH block error rate are satisfied. In this way, removing channel estimation and noise estimation from a PDCCH demapping path may reduce the PDCCH decode time, whereby the UE may trigger a microsleep sooner to increase a sleep ratio and thereby increase power savings.

Aggressive extra microsleep using stale channel estimate and noise estimate to decode control channel

Certain aspects of the present disclosure provide techniques for reducing a quantity of data sent carrier aggregation (CA) related capability reporting by a UE operating in a cell using full dimension multiple-input multiple-output (FD-MIMO) techniques. In an exemplary method, a base station obtains a relative weight of baseband processing for a component carrier (CC) configured for full-dimension multiple-input multiple-output (FD-MIMO) communications for a user equipment (UE); determines, based on the relative weight, to enable FD-MIMO downlink (DL) transmissions to the UE via the CC; and transmits an FD-MIMO transmission via the CC to the UE.

Full dimension multiple-input multiple-output baseband capability indication

Embodiments include systems and methods for performing selection of a transport format combination by a device processor of a wireless communication device. The device processor may determine whether radio frequency self-jamming interference is detected at the receiver of the wireless communication device. The device processor may calculate an average transmit power reduction in response to determining that radio frequency self-jamming interference is detected at a receiver of the wireless communication device. The device processor may select a transport format combination based on the calculated average transmit power reduction, and may use the selected transport format combination to transmit data to a communication network.

Transport format combination selection during self-jamming interference

One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.

Executing a hardware simulation and verification solution

The present disclosure presents methods and apparatuses for enhanced received signal processing using signal-based channel impulse response (CIR) estimation. For example, according to an example method presented herein, a user equipment (UE) or a component therein may receive a signal corresponding to a transmitted signal sent by a network entity, wherein the transmitted signal comprises at least a data channel, estimate chip contents of the transmitted signal, based on the received signal including the data channel, to obtain estimated chip contents, and compute an estimated channel impulse response (CIR) based on at least the estimated chip contents. Based on this estimated CIR, the UE may thereafter reprogram a received signal reconstruction filter, perform interference cancellation procedures, and/or adjust one or more equalizer taps. By performing such functions, the UE may exhibit improved communication characteristics and enable a more robust user experience.

Methods and apparatuses for enhanced received signal processing based on a data-signal-aided channel impulse response estimation

Method and apparatus for executing a hardware simulation and verification solution

A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a path through combinational logic in a design of the IC chip, starting from an output port of a first scan cell and ending in an input port of a second scan cell. If the first and second scan cells receive a common scan enable signal, then the computer generates at least a portion of the computer program, i.e. software to perform simulation of propagating a signal through the path conditionally, for example when the common scan enable signal is inactive and alternatively to skip performing simulation when the common scan enable signal is active. The computer stores the portion of the computer program in memory, for use with other such portions of the computer program.

Enhancing speed of simulation of an IC design while testing scan circuitry

A method and system for reducing the time required for execution of the dynamic timing simulation for a logic simulator. For a logic circuit simulator having a compilation phase and a runtime phase, a delay assessment is performed during the compilation phase in order to identify storage elements that are exempt from possible timing violations at runtime. The runtime timing checks are removed from the exempt storage elements, thereby reducing the runtime calculation effort. Additionally, combinational portions of the circuit that drive the exempt storage elements are examined for element delays that can be effectively eliminated (e.g., zero delayed) from the runtime calculations, thereby providing a further reduction in the computational overhead via the use of cycle based simulation for these.

System and method for enhancing the speed of dynamic timing simulation using delay assessment at compile time

A voltage regulator includes an output node and first and second regulator circuits. The first regulator circuit generates a first regulated voltage on the output node when a supply voltage equals or exceeds a predetermined threshold, and the second regulator circuit generates a second regulated voltage on the output node when the supply voltage is less than the predetermined threshold.

Voltage regulator operable over a wide range of supply voltage

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San Jose, CA, United States of America

Manish Jain