Lsi Logic Corporation

Maniam B Alagaratnam

Chok J Chia

Kishor V Desai

Qwai Hoong Low

Patrick J Variot

Seng-Sooi Allen Lim

Sunil A Patel

John Pierre McCormick

Sarathy Rajagopalan

Aritharan Thurairajaratnam

Manickam Thavarajah

Wee Keong Liew

Seng Sooi Lim

Teresa Dalao

A semiconductor package comprising a packaging substrate, a semiconductor die mounted with the substrate, a heatspreader, and a multi-layer heat transfer element arranged between the semiconductor die and the heat spreader to enable thermal communication between the die and the heat spreader is disclosed. The multi-layer heat transfer element includes a core spacer element sandwiched between a first layer of thermally conductive reflowable material and a second layer of thermally conductive reflowable material. Also disclosed are methods for forming such semiconductor packages and for forming multilayer heat transfer elements.

Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package

A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.

Multi chip module assembly

A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer. The substrate is immersed in a second electrolytic plating bath, and a second electrical potential is applied between the first layer and the second electrolytic plating bath, thereby causing the formation of a third layer of a third electrically conductive material on the second layer. The masking layer is removed from the substrate to expose the second portions of the first layer, and the exposed second portions of the first layer are removed to form discrete contact pads from the first portions of the first layer and the overlying second layer and third layer.

Method of forming electrolytic contact pads including layers of copper, nickel, and gold

The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.

Interposer for semiconductor package assembly

An integrated circuit package is provided that allows high density routing of signal lines. A substrate of the package may include an upper surface upon which a bonding finger resides, a lower surface upon which a solder ball resides, and a signal conductor plane on which a signal trace conductor resides a dielectrically spaced distance between the upper surface and the lower surface. A first via may extend perpendicularly from the upper surface, connecting the bonding finger to the first portion of the signal trace conductor. A second via may extend perpendicularly from the lower surface, connecting the solder ball to the second portion of the signal trace conductor. The routing of the vias and signal trace conductors may cause the signal lines to either fan into or away from the area of the integrated circuit package adapted to receive the integrated circuit.

Integrated circuit package substrate with high density routing mechanism

A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bottom surface of the top die is separated from the top surface of the bottom die by an interposer, which creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. Each of a plurality of wires, which are electrically connected to the bottom die, runs through this space (i.e. runs between the top surface of the bottom die and the bottom surface of the top die), thereby permitting (if desired) the top die to be at least as large as the bottom die.

Dual chip in package with a wire bonded die mounted to a substrate

A test fixture for a ball grid array package is disclosed that includes a test ball grid array package having a plurality of coarse pitch contacts formed on a coarse pitch surface of the test ball grid array package and a plurality of wafer bumps formed on a fine pitch surface of the test ball grid array package and an interposer coupled to the plurality of wafer bumps formed on the fine pitch surface of the test ball grid array package for coupling to a plurality of wafer bumps formed on a fine pitch surface of a subject ball grid array package.

Test fixture for flip chip ball grid array circuits

Provided is an interposer tape which provides electrical communication between a die and a packaging substrate. The dimensions of the interposer tape may vary to accommodate a variety of die sizes for the same packaging substrate. The interposer tape includes an array of traces. A first set of wire bonds is formed between the array of traces and the die. A second set of wire bonds is formed between the array of traces and the packaging substrate.

Interposer tape for semiconductor package

A semiconductor package (,) includes a bondable aluminum heatspreader (,) made from anodized aluminum, thereby forming an anodization layer (,) on the surface of the heatspreader. Portions of the anodization layer are removed, e.g., by grinding, in order to provide an attachment area (,) to which a wire (,) or beam may be bonded in order to electrically connect the heatspreader to a desired voltage potential, such as a ground potential or a positive or negative potential. The heatspreader is thermally bonded to a semiconductor die (,) housed within the package. The anodized aluminum heatspreader thus not only removes and dissipates heat from the semiconductor die, but also functions as a voltage or ground plane within the semiconductor package.

Bondable anodized aluminum heatspreader for semiconductor packages

One aspect of the invention relates to a flip-chip semiconductor package. In one version of the invention, the flip-chip semiconductor package includes a package substrate having an upper surface, a lower surface and a plurality of conductive traces, the upper surface having an upper plurality of electrical contacts coupled to the conductive traces, the lower surface having a lower plurality of electrical contacts coupled to the conductive traces, the lower plurality of electrical contacts being attachable to electrical contacts on a printed circuit board; a semiconductor die having an active surface and a non-active surface, the active surface having a plurality of circuit elements and a plurality of bond pads formed thereon, the bond pads being attached to the upper plurality of electrical contacts by solder bumps, the non-active surface having a plurality of grooves formed thereon; and a heat sink attached to the non-active surface of the semiconductor die.

Grooved semiconductor die for flip-chip heat sink attachment

A method of electroplating a high density integrated circuit (IC) substrate using a conductive elastomer including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces with conductive trace lands formed on its surface. Covering only the traces (not the trace lands) with a plating resist and exposing portions of the conductive traces. Inserting the IC substrate into a electroplating fixture. Engaging a conductive elastomer to the IC substrate, covering the plurality of conductive traces and electrically connecting all of the traces together. Electroplating the trace lands on the IC substrate with conductive material (such as gold or nickel) by using the conductive elastomer as the electrical connection to the trace lands (via the exposed metal traces). Disengaging the conductive elastomer after electroplating is finished and removing the IC substrate from the electroplating fixture.

Electroplating fixture for high density substrates

A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i.e., a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant. The liquid encapsulant is preferably a C4 underfill material. By injecting the liquid encapsulant under pressure, the amount of time required to dispense the liquid encapsulant is reduced as well as the number of voids present in the liquid encapsulant. Following at least partial curing of the encapsulant, the mold sections are separated, and the packaged semiconductor device is removed. When fully cured and hardened, the encapsulant adheres to the adjacent surfaces of the integrated circuit and the substrate, essentially interlocking the surfaces.

System and method for packaging an integrated circuit using encapsulant

A molded tape ball grid array package has a base structure including a heat conductive substrate and flex tape extending from opposing regions on a surface of the substrate with molded plastic material between the flex tape and the substrate. The flex tape has at least one conductive metal lead pattern which can be positioned on a side of the tape facing the substrate with a plurality of apertures exposing the conductive lead pattern from an opposing side of the tape for solder ball bonding. A semiconductor integrated circuit chip is mounted to a central portion of the substrate between the opposing regions of the flex tape with wire bonding interconnecting bond pads on the chip to the metal lead pattern. The chip and wire bonding are then encapsulated on the substrate. The structure is economical and permits high power dissipation from an integrated circuit. The molding process in fabricating the integrated circuit package is economical and readily implemented using injection molding.

High power dissipating tape ball grid array package

Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.

Growing community of inventors

Cupertino, CA, United States of America

Maniam B Alagaratnam