Texas Instruments Corporation

Texas Instruments Incorporated Deutschland, Gmbh

Manfred Schiekofer

Badih El-Kareh

Philipp Steinmann

Scott G Balster

Jeffrey A Babcock

Angelo Pinto

Scott Balster

Hiroshi Yasuda

Thomas Scharnagl

Pietro Foglietti

Robert Maier

Carl David Willis

Gregory Eric Howard

Alfred Haeusler

Wolfgang Heinz Schwartz

Wolfgang Ploss

Klaus Schimpf

Michael Waitschull

Alfred Hausler

Michael Kraus

A system for controlling an epitaxial growth process in an epitaxial reactor. The system includes a processor for setting up a modeled output parameter value as a linear function of the actual output parameter value and a second set of thermocouple offset parameter values. The processor also determines a distance between a target output parameter value and the modeled output parameter value.

Controlling an epitaxial growth process in an epitaxial reactor

A method of controlling an epitaxial growth process in an epitaxial reactor. The method includes optimizing the thermocouple offset parameter for a second run by setting up a modeled output parameter value as a linear function of the actual output parameter value, and a second thermocouple offset parameter value.

Method of controlling an epitaxial growth process in an epitaxial reactor

Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.

Method of forming an electrical contact between a support wafer and the surface of a top silicon layer of a silicon-on-insulator wafer and an electrical device including such an electrical contact

A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.

Bipolar transistor

An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection

An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (), each having a buried collector region ('). A carbon-bearing diffusion barrier () is disposed over the buried collector region (&#x2032;), to inhibit the diffusion of dopant from the buried collector region (&#x2032;) into the overlying epitaxial layer (). The diffusion barrier () may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks () may be used to define the locations of the buried collector regions (&#x2032;) that are to receive the carbon; for example, portions underlying eventual collector contacts () may be masked from the carbon implant so that dopant from the buried collector region (&#x2032;) can diffuse upward to meet the contact (). MOS transistors () including the diffusion barrier () are also disclosed.

Control of dopant diffusion from buried layers in bipolar integrated circuits

A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.

Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer

In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regionsby epitaxial deposition of crystalline silicon-germanium layers. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layerscan be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers

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Freising, Germany

Manfred Schiekofer