Infineon Technologies Ag

Infineon Technologies Austria Ag

Manfred Mengel

Joachim Mahler

Khalil Hosseini

Franz-Peter Kalz

Henrik Ewe

Horst Theuss

Edward Fuergut

Ralf Otremba

Gottfried Beer

Bernhard Winkler

Jochen Dangelmaier

Oliver Eichinger

Andreas Niederhofer

Josef Hoeglauer

Klaus Schiess

Ivan Nikitin

Alexander Heinrich

Markus Brunnbauer

Frank Pueschner

Alfred Haimerl

Edmund Riedl

Evelyn Napetschnig

Klaus Pressel

Thomas Behrens

Thomas Spoettl

Holger Torwesten

Stephan Schaecher

Thomas Wowra

Lim Fong

Klaus Schmidt

Nina Wenger

Holger Tamme

Steffen Orso

Klaus Mueller

Xaver Schloegel

Alexander Breymesser

Swee Kah Lee

Juergen Schredl

Stefan Landau

Reimund Engl

Wolfram Hable

Soon Lock Goh

Frank Puschner

Christian Kasztelan

Jürgen Högerl

Christof Matthias Schilz

Jurgen Fischer

Edward Fürgut

Louis Vervoort

Stefan Schmid

Johannes Hankofer

Johannes Hankhofer

Beer Gottfried

A method includes forming a plurality of first semiconductor mesa structures at a first semiconductor substrate. The first semiconductor substrate has a first conductivity type. The method further includes forming a plurality of second semiconductor mesa structures at a second semiconductor substrate. The second semiconductor substrate has a second conductivity type. The method further includes providing a glass substrate between the first semiconductor substrate and the second semiconductor substrate. The method includes connecting the first semiconductor substrate to the second semiconductor substrate so that at least a portion of the glass substrate is located laterally between the first semiconductor mesa structures of the plurality of first semiconductor mesa structures and the second semiconductor mesa structures of the plurality of second semiconductor mesa structures.

Thermoelectric devices and methods for forming thermoelectric devices

Method for manufacturing an electronic semiconductor package, in which method an electronic chip () is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

Electrically insulating thermal interface on the discontinuity of an encapsulation structure

A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

Chip arrangements

In various embodiments, a wafer box is provided. The wafer box may include a housing with a receiving space for receiving a stack comprising a plurality of wafers, each arranged above a housing base. The wafers are to be arranged with their main surfaces parallel to the housing base. The receiving space is delimited by the housing base and side walls arranged thereon. The wafer box may further include at least one base opening, arranged in the housing base, for receiving a guide structure of a wafer stacking aid. The guide structure is to be arranged in such a way that, on a side of the housing base on which the side walls are arranged, it extends out of the housing base in order to limit tilting of a wafer raised or lowered in the receiving space in a manner guided by the guide structure.

Wafer box, wafer stacking aid, wafer carrier, wafer transport system, method for loading a wafer box with wafers and method for removing wafers from a wafer box

Various embodiments provide a wafer box. The wafer box may include a housing with a receiving space for receiving at least one wafer arranged above a housing base, at least one fixing structure which is connected to the housing base and which extends from the housing base, and at least one fixing device which is fastenable to the at least one fixing structure at a variable distance from the housing base. The fixing device and the fixing structure are designed such that the at least one wafer for arrangement in the receiving space can be fixed in a position by means of the at least one fixing device fastened to the fixing structure.

Wafer box, method for arranging wafers in a wafer box, wafer protection plate and method for protecting a wafer

A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

Method for manufacturing a chip arrangement including a ceramic layer

A micromechanical semiconductor sensing device is disclosed. In an embodiment the sensing device includes a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, the piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal.

Micromechanical semiconductor sensing device

A solder alloy is providing, the solder alloy including zinc, aluminum, magnesium and gallium, wherein the aluminum constitutes by weight 8% to 20% of the alloy, the magnesium constitutes by weight 0.5% to 20% of the alloy and the gallium constitutes by weight 0.5% to 20% of the alloy, the rest of the alloy including zinc.

Solder alloys and arrangements

Micromechanical semiconductor sensing device comprises a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, said piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal.

An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Electronic component

A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit

An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the electronic chip, and a periphery connection structure electrically coupled to the redistribution structure and being configured for connecting the electronic component to an electronic periphery, wherein at least one of the electrically conductive mounting structure and the electrically conductive redistribution structure comprises electrically conductive inserts in an electrically insulating matrix.

Electronic component with electronic chip between redistribution structure and mounting structure

In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer.

Semiconductor device including a polymer disposed on a carrier

An electrical component that includes a substrate and a polymeric layer oriented in working relation with the substrate, the polymeric layer including a low molecular mass polyimide.

Low viscosity polymeric printing solutions and electronic components bearing polyimide based upon the low viscosity polymeric printing solutions

Growing community of inventors

Bad Abbach, Germany

Manfred Mengel