Samsung Electronics Co., Ltd.

Man-Jae Yang

Byung-Hoon Jeong

Young-Don Choi

Dong-Su Jang

Go-Eun Jung

Jeong-Don Ihm

Jeong-don Ihm

A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Growing community of inventors

Hwaseong-si, South Korea

Man-Jae Yang