Motorola Corporation

Mamoru Tomozane

H Ming Liaw

Bertrand Francis Cambou

A SIMOX structure having a reduced number of defects is formed by performing a two step anneal. In one embodiment, a conventional anneal is followed by an H.sub.2 /Si anneal. The conventional anneal first densifies the buried oxide layer in order to make the oxide less reactive with hydrogen. The H.sub.2 /Si anneal forms a quasi-equilibrium at the superficial semiconductor layer surface, thus there is no etching of the silicon surface and there is only a negligible amount of silicon deposition. The H.sub.2 reacts with the oxide precipitates and dissolves them. In a second embodiment the two step anneal comprises a low temperature H.sub.2 anneal followed by a conventional anneal. At low temperature, H.sub.2 can diffuse through silicon, but is much less reactive. Thus, etching of the superficial silicon and silicon dioxide buried layer is minimal. The conventional anneal is at a higher temperature, thus H.sub.2 can react with the oxygen precipitates to remove them.

Method of forming a SIMOX structure

A non-silicon substrate is bonded to a silicon substrate with a stress-relief layer between the non-silicon substrate and the silicon substrate. The stress-relief layer reduces the stress between the non-silicon substrate and the silicon substrate. The stress is created by the difference in the thermal expansion coefficients of the two materials. The stress-relief layer may be a low melting point metal, a semiconductor layer having its thermal expansion coefficient close to the thermal expansion coefficient of the non-silicon substrate. The silicon substrate and/or the non-silicon substrate may have a silicon dioxide layer formed thereon such that the silicon dioxide layer is adjacent to the stress-relief layer.

Non-silicon and silicon bonded structure and method of manufacture

A thick buried insulating layer is formed by employing a multiple semiconductor layer growth/implant/anneal cycle. A first buried insulating layer is formed in a semiconductor substrate by implanting a dopant which reacts with the substrate to form an insulating layer and then annealing the substrate. Subsequently, a thin semiconductor layer is grown on the surface of the substrate. This is followed by a second implantation of the dopant which reacts with the substrate to form an insulating layer and an anneal to form a second buried insulating layer. The two buried insulating layers may be continuous to form a single, thick buried insulating layer or may be discontinuous to form two buried insulating layers separated by a semiconductor layer. The cycle may be repeated until a desirable thickness of the buried insulating layer is achieved or until a desirable number of buried insulating layers are formed.

Method of fabricating buried insulating layers

Silicon and non-silicon semiconductor devices are fabricated on a single chip by bonding a silicon wafer to a non-silicon semiconductor substate. Portions of the non-silicon semiconductor substrate are selectively etched to expose the silicon wafer. Semiconductor devices may then be formed in the silicon wafer and on the non-silicon semiconductor substrate. Alternatively, selective epitaxial silicon may be grown where the non-silicon semiconductor substrate was removed. In another embodiment, a non-silicon semiconductor substrate having wells formed therein is bonded to a silicon wafer. The non-silicon semiconductor substrate is then polished until openings are provided to the silicon wafer. Further processing is carried out as described above.

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Scottsdale, AZ, United States of America

Mamoru Tomozane