Macronix International Co., Ltd.

Harvatek Corporation

Other

Mam-Tsung Wang

Wenpin Lu

Tao-Cheng Lu

Ming-Shang Chen

Meng-Hwang Liu

Ying-Che Lo

Chia-Shing Chen

Shyi-Ming Pan

Ming-Hung Chou

Chun-Jung Lin

Tao Cheng Lu

Chun-Yi Yang

Chin-Hsi Lin

Ful-Long Ni

Ping-Lung Wang

Baw-Chyuan Lin

Jui-Chin Chang

Cheng-Shang Lai

Chung-Ju Chen

Chin-Yi Huang

Chia-Hsing Chen

Chen-Shang Lai

Chung Ju Chen

Bing-Ying Wang

Ping-Ying Wang

Ming-Jye Chiou

Chien-Sing Lee

Shi-Charng Ai

A light source assembly includes a plurality of cells and a driving circuit. Each of the cells includes a transistor and a light source. The transistor includes a drain region that serves as a cathode of the light source. The driving circuit is configured to drive the cell. An optical sensor cell and a method for manufacturing thereof are also disclosed.

Light source assembly, optical sensor assembly, and method of manufacturing a cell of the same

A light-emitting diode (LED) assembly comprises a plurality of LED cells and a driving circuit. Each of the LED cells includes an LED and a transistor. The LED includes first and second LED layers and an LED electrode. The first LED layer includes a III-V compound semiconductor. The second LED layer is over the first LED layer. The LED electrode is over the second LED layer. The first LED layer is free of an LED electrode. The transistor includes a drain region connected to the first LED layer. The driving circuit is configured to drive the LED cells.

Light-emitting diode (LED) assembly and method of manufacturing an LED cell of the same

Current source component with process tracking characteristics for compact programmed Vt distribution of flash EPROM

An ESD protection structure for protecting an internal circuit comprising a primary protection device, a secondary protection device, and a substrate pickup is presented. The primary protection device and secondary protection device share a common source, and this common source implementation lowers the trigger voltage of the primary protection device to be about the same as the trigger voltage of the secondary protection device, thereby eliminating the need to use an isolation resistor between the primary and secondary protection devices.

Electrostatic discharge input protection for reducing input resistance

The present invention provides a method of performing optical proximity corrections of a photo mask pattern by using a computer. The photo mask pattern is formed on a photo mask which is used when performing photolithography for forming a predetermined original pattern by exposing a photo-resist layer in a predetermined area of a semiconductor wafer. The photo mask pattern is divided into a plurality of rectangular blocks. Each block can be bright or dark, and a least one side and two corners of the block are shared with another block. Each of shared corners is checked to find corners which may be affected by an optic proximity effect, and those corners are modified so as to prevent them from being affected by the optic proximity effect.

Method of performing optical proximity corrections of a photo mask pattern by using a computer

Mask ROMS with fixed code implantation and associated integrated circuits are described. An integrated circuit has a Mask ROM including: an array of memory cells including a first bank of memory cells and a second bank of memory cells, and the first bank of memory cells separated from the second bank of memory cell by a set of select lines, and the first bank of memory cells and the second bank of memory cells includes at least one fixed code implanted memory cell column. The use of fixed code implantation results in a single current path during the reading of a given memory cell and permits the size of the corresponding device to be reduced and have better topography. The Mask ROM provides additional advantages because the use of the same select transistors for two banks reduces the overhead of select transistors for a given size of array, the use of only one sense amplifier per block reduces the overhead of sense amplifiers for a given size of array, and the use of odd and even word line decoders divides the memory cell array into a number of banks.

Multi level mask ROM with single current path

A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and suicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

Silicide blocking process to form non-silicided regions on MOS devices

An apparatus for programming selected floating gate storage transistors in a data storage device includes a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate. Circuitry, coupled to the selected floating gate storage transistor, maintains drain current of the selected floating gate transistor at a substantially stable value during programming. In one example, the circuitry is a stable current source in parallel with a load coupled to the source of the selected floating gate transistor. The stable current source, in one embodiment, is a current mirror designed to supply a fixed current level. The load may be a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited. The load may be a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.

Apparatus and method for programming of flash EPROM memory

The present invention provides a method of writing a set of binary codes into a ROM. The method is performed by forming a first photo mask and a second photo mask according to an original first code pattern, an original second code pattern, and a set of binary codes to be written into the ROM. Final first and second code patterns are formed by coupling the binary codes to be written with the original first and second code patterns by using a Boolean logical OR operation. The first and second photo masks are formed according to the final first and second code patterns. The first photolithographic process is performed using the first photo mask, and the first ion implantation process is performed; the second photolithographic process is performed using the second photo mask, and the second ion implantation process is performed. Thus the set of binary codes is written into the ROM completely and correctly.

Method of forming a binary code of a ROM

A self-protected output driver for an integrated circuit utilizing cascode configured MOSFET transistors is formed in a single active region, allowing a smaller layout area without sacrificing performance. Furthermore, the driver is laid out according to a standard cell layout and is adaptable for a variety of output driving specifications according to the need of a particular implementation. A doped region having a first conductivity type is formed in the substrate. A plurality of sets of cascode connected transistors having channels in the doped region is included. Sets of cascode connected transistors in the plurality include a first diffusion region, a second diffusion region on a first side of and separated from the first diffusion region by a channel of a first transistor, a third diffusion region on a second side of and separated from the first diffusion region by a channel of the second transistor, a fourth diffusion region on a first side of and separated from the second diffusion region by a channel of a third transistor, a fifth diffusion region on a second side of and separated from the third diffusion region by a channel of a fourth transistor. Gate structures are formed over the channels of the first, second, third and fourth transistors. An interconnect structure couples the first diffusion region to the contact pad, the fourth and fifth diffusion regions to the second supply terminal, the gate structures of the first and second transistors to a first supply terminal, the gate structure of the third transistor to a selected one of the second supply terminal and a signal source, and the gate structure of the fourth transistor to a selected one of the signal source and the second supply terminal. The structure acts typically as a pull-down stage for an output driver on an integrated circuit. A pull-up transistor is included in the complete circuit. The diffusion regions between the first and third transistor and between the second and fourth transistor are formed without silicide.

Self protected stacked NMOS with non-silicided region to protect

A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a first and second column of floating gate cores on the dielectric; (3) implanting a first dopant adjacent the second column and displaced from the first column, the first dopant having a second conductivity type opposite the first conductivity type; (4) forming floating gate sidewalls in contact with the floating gate cores; (5) implanting a second dopant between the floating gate sidewalls, the second dopant having the second conductivity type; (6) forming a thermal oxide between the first and second column of floating gate cores such that oxide encroachments are formed below the floating gate cores of the first and second column and the first dopant is separated from the second column of floating gate cores by the first dielectric and the second dopant is separated from first column of the floating gate cores by the oxide encroachment; and (7) completing formation of control gate dielectric and control gates. The presence of tunneling and non-tunneling connections on the source and drain side of each cell improves the isolation between adjacent memory cells and minimizes the disturb problem.

Virtual ground flash cell with asymmetrically placed source and drain

A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and silicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

A device and method of operation for an improved erase-verify device in which the non-selected cells, within a bit line column of an array of cells, remain inactive. Only the active cell is verified with minimum bit line column leakage associated with the operation of erase verification. Erase verification for a memory array is achieved by applying a source voltage (generally positive) to the common source line associated with a column of cells in the array. This will raise the threshold voltages of the cells (through the body effect of the semiconductor device) to a level higher than the predetermined minimum erased threshold voltage. The non-selected wordlines are coupled to a reference level below the threshold level of the cell (e.g. ground), and the selected wordline is coupled to a positive voltage which is a function of the source voltage. The source voltage is also added to the drain source voltage. The source voltage thereby serves as a feedback input to both the wordline and bit line inputs. Thereafter, a fixed drain-to-source bias is applied to the selected bit line column to conduct current for verification of the cell. The source voltage feedback allows the wordline voltage to be adjusted so that read current through the selected cell can be maintained at a desired level. Using this approach, the bit line column leakage caused by over-erased cells can be effectively suppressed, and an accurate verification result can be achieved.

Device and method for suppressing bit line column leakage during erase

A mask read-only-memory cell structure without ROM code implantation is presented. By using double polysilicon technology, ROM code cells which store data '0' can be replaced by cells with double polysilicon layers and an insulating layer between them. Normal cells with double polysilicon layers but without an insulating layer between them form normal cells store data '1'. According to the invention, further scaling of mask ROM is possible and operating condition can be released because of high junction breakdown voltage. Furthermore, the double polysilicon technology makes redundancy circuit more easily to implement.

Cell structure for mask ROM

A method for programming an analog/multi-level flash memory array, which insures fast programming to substantially all of the cells in the array, without over-programming, is based on providing a pattern of program retry pulses which have respective pulse widths and pulse heights which vary according to a pattern. The pattern includes three stages which program and verify cell threshold voltages with different program verification margins so that an accurate cell threshold voltage can be achieved for each cell.

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Hsinchu, Taiwan

Mam-Tsung Wang