Stmicroelectronics S.a.

France T&eacute;l&eacute;com

France Telecom

Malgorzata Jurczak

Thomas Skotnicki

Hervé Jaouen

Didier Dutartre

Michel Haond

Herv&eacute; Jaouen

Catherine Mallardeau

A magnetic sensor includes a thin deformable membrane made of a conductive material forming a first plate of a capacitor which conducts an electric current therethrough. A second capacitor plate of the capacitor includes a doped region of a semiconductor substrate. A layer of a gaseous dielectric separates the two plates. The membrane deforms due to the effect of the Lorentz force generated by a magnetic field lying in the plane of the membrane and perpendicular to the lines of current being conducted therethrough. In addition, a process for fabricating this magnetic sensor is also provided as well as a device for measuring a magnetic field using the magnetic sensor.

Magnetic sensor of very high sensitivity

The invention concerns a method which consists in forming on a substrate () coated with a dielectric material layer () provided with a window (), a stack of successive layers alternately of germanium or SiGe alloy () and polycrystalline silicon (); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material () on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (). The invention is useful for making dynamic random-access memories.

Method for making a stack of capacitors, in particular for dynamic random access memory [DRAM]

Very high sensitivity magnetic sensor

A method of fabricating an SON structure semiconductor device is described. There is formed, on a silicon substrate, a stack of layers comprising first and second successive combinations. Each successive combination has a bottom silicon-germanium alloy (Site) layer and a top silicon layer. In a conventional way, a gate dielectric layer, a gate, spacers, source and drain regions, and an external passivating layer are formed by ionic implantation. A vertical hole is formed in the gate as far as the bottom Site layer to etch a part of the Site layers to form tunnels. The walls of the hole and the tunnels are then internally passivated so that the tunnels can remain empty or be filled.

Method for lateral etching with holes for making semiconductor devices

A method of fabricating a semiconductor device consisting of a silicon substrate on which is formed a stack of layers is described. The stack may have successively at least one first and one second combination. Each combination may consist, with reference to the substrate, of a thin bottom SiGe layer and a thin top silicon layer. A thin silicon dioxide film ( ) is formed on the thin top silicon layer of the second combination so that the layer concerned supports the layers of the stack on at least two opposite lateral sides of the stack. Successive selective lateral etching of the SiGe layers is then carried out to form tunnels which are filled with a dielectric material.

Method for making a semiconductor device comprising a stack alternately consisting of silicon layers and dielectric material layers

A transmitter or receiver includes several transducers formed opposite an aperture in a package. Each transducer includes a deformable semiconductor membrane that is capable of conducting current. The membrane is separated from a substrate zone by a cavity. This allows the membrane to deform due to the effect of an acoustic pressure or of a Lorenz force.

Integrated sound transmitter and receiver, and corresponding method for making same

A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.

Method for making a silicon substrate comprising a buried thin silicon oxide film

The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

Process for fabricating a network of nanometric lines made of single-crystal silicon and device obtained

A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor

A method is provided for fabricating a semiconductor device having a gate-all-around architecture. A substrate is produced so as to include an active central region with an active main surface surrounded by an insulating peripheral region with an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A fist layer of Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure defines a tunnel with a corresponding part of the active main surface. A thin layer of a dielectric material that does not fill the tunnel is formed on the external and internal surfaces of the bridge structure and on the side walls. A conducting material is deposited so as to cover the bridge structure and fill the tunnel, and the conducting material is masked and etched in order to form a gate-all-around region for the semiconductor device. Also provided is a semiconductor device having a gate-all-around architecture.

Growing community of inventors

Grenoble, France

Malgorzata Jurczak