Texas Instruments Corporation

Raytheon Company

Raytheon Ti Systems, Inc.

Drs Technologies, Inc.

Malcolm John Bevan

Husam N Alshareef

Haowen Bu

Hiroaki Niimi

Rajesh B Khamankar

Luigi Colombo

Mark H Somervell

Brian Keith Kirkpatrick

April Gurba

Clinton L Montgomery

Antonio L P Rotondaro

Hung-Dah Shih

Mark R Visokay

Donald F Weirauch

Ajith Varghese

Anand T Krishnan

Sebastian R Borrello

William L McCardel

Mark V Wadsworth

Douglas E Mercer

Men-Chee Chen

Herbert F Schaake

Carlos A Castro

Glenn H Westphal

Cathy A Chancellor

Kent R Carson

Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

System and method for mitigating oxide growth in a gate dielectric

A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.

Thermal treatment of nitrided oxide to improve negative bias thermal instability

CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Integrated circuits with composite gate dielectric

The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Post high voltage gate oxide pattern high-vacuum outgas surface treatment

The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

Dual-gate integrated circuit semiconductor device

Post high voltage gate dielectric pattern plasma surface treatment

Growing community of inventors

Dallas, TX, United States of America

Malcolm John Bevan