Hitachi, Ltd.

Texas Instruments Corporation

Hitachi Ulsi Engineering Corp.

Hitachi Microcomputer Eng. Ltd.

Hitachi Microcomputer Hitachi, Ltd. & Engineering, Ltd.

Makoto Saeki

Shunichi Sukegawa

Yukihide Suzuki

Shuji Ikeda

Osamu Minato

Hideaki Nakamura

Sho Yamamoto

Kiyoshi Nagai

Masaaki Kubotera

Yasuo Yoshitomi

Masakazu Aoki

Masahiro Iwamura

Tatsumi Yamauchi

Hiromasa Noda

Katsuhiro Shimohigashi

Tsugio Takahashi

Yoshitaka Tadaki

Osamu Tsuchiya

Katsuyuki Sato

Shinji Nishihara

Hidetoshi Iwai

Toshihiro Sekiguchi

Masayuki Nakamura

Hideaki Uchida

Jun Murata

Keiichi Yoshizumi

Youji Idei

Katsuo Komatsuzaki

Kazushi Fukuda

Kanehide Kenmizaki

Soichiro Hashiba

Fumiyuki Kanai

Tadashi Tachibana

Hisae Yamamura

Yasuhito Ichimura

Yoritaka Saitoh

Takeshi Fukazawa

Ken Saitoh

Chisa Makimura

Tadashi Abe

Seiichi Ariga

Yoojoon Moon

An address decoder with low power consumption of feedthrough current, leakage current, etc. Address bits AY0.sub.0 -AY0.sub.7 are respectively supplied to n-type gate terminals of CMOS transfer gates C.sub.0 -C.sub.7 and the gate terminals of PMOS transistors P.sub.0 -P.sub.7. Inverted address bits AY0.sub.0- -AY0.sub.7- are supplied to p-type gate terminals of the CMOS transfer gates C.sub.0 -C.sub.7. Enable signals AY3.sub.p, AY6.sub.q are respectively input to both input terminals of a NAND circuit 10. The output terminals of NAND circuit 10 are connected to the input terminals of CMOS transfer gates C.sub.0 -C.sub.7. The output terminals of CMOS transfer gates C.sub.0 -C.sub.7 are connected to the input terminals of the drivers D.sub.0 -D.sub.7 and the drain terminals of the PMOS transistors P.sub.0 -P.sub.7 via a node F.sub.0 -F.sub.7. The source terminals of PMOS transistors P.sub.0 -P.sub.7 are connected to a power supply voltage V.sub.cc, for example of 3.3 V. The output terminals of drivers D.sub.0 -D.sub.7 are connected to Y-address lines YS.sub.0 -YS.sub.7.

Address decoder

A word line leak check test for a semiconductor memory arranged as a matrix which includes word lines and y-selection lines. First, a RAS signal is enabled while a prescribed row address is input, and word line 22 is driven to the Vpp level. Then, when the CAS signal is enabled, the voltage source is disconnected from word line 22, and word line 22 floats. Two bits for the column address are disregarded, and the Y selection signal line 23 is decoded without those 2 bits. By this means, 4 y-selection signal lines 23 are simultaneously enabled. When this condition has been maintained for a prescribed time T, a delayed write operation is conducted, and then it is determined whether the data has been correctly stored in memory cell 24.

Method for testing word line leakage in a semiconductor memory device

An address access path control circuit designed for shorter access time and small the layout area with low power consumption and noise. Our control circuit has a latching circuit LMO2A, a main output circuit MO3, and a common-bus driving circuit CBD for holding the level of a pair of common-buses CB/CB.sub.-- at the ground level during a prescribed period of time in which address transition takes place while the read data is output to common-buses CB/CB.sub.-- at a timing corresponding to the address signal. A data output buffer DO-BUF outputs to the outside the data transmitted from common-buses CB/CB.sub.-- to data output lines OD/OD.sub.-- in response to the input of control signal DOE. A control signal DOE is input to data output buffer DO-BUF during the period in which data output lines OD/OD.sub.-- are at the ground level.

Address access path control circuit

A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.

Semiconductor memory device

A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.

Dynamic RAM

A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.

Dynamic memory device, a memory module, and a method of refreshing a

Negative characteristic MISFETs, which are of the same channel conductivity type and which have different threshold voltages, are formed in a doped silicon thin film deposited over a substrate and are connected in channel-to-channel series with each other. The pair of series-connected negative characteristic MISFETs, a resistive element, an information storage capacitive element and a transfer MISFET constitute an SRAM memory cell. Equivalently, a negative characteristic MISFET having a current-voltage characteristic defined by a negative resistance curve can be used in lieu of the pair of series-connected negative characteristic MISFETs in the formation of the individual memory cells of the SRAM. The negative resistance curve of the negative characteristic MISFET is shaped such that the linear current-voltage characteristic curve corresponding to the resistive element of the memory cell intersects the negative resistance curve at at least three location points. The negative characteristic MISFET, like the pair of series-connected negative characteristic MISFETs, has an active region formed in a doped thin film silicon (polycrystalline silicon) layer insulatedly above a substrate main surface. The resistive element is also formed in a thin film silicon layer either integrally with the negative characteristic MISFET or in a separate thin film silicon layer and in series electrical connection with the negative characteristic MISFET.

Semiconductor device having a two-channel MISFET arrangement defined by

In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.

Method for manufacturing semiconductor integrated circuit device having

In case an address is to access a defective memory cell, a defective memory cell in a memory cell area contained in one of paired memory mats is selected in parallel with a redundant memory cell in a redundant memory cell area contained in the other memory mat. At this time of selecting the redundant main word line for selecting the redundant memory cell, there is not required the logical operation for deciding whether or not the redundant use of the access address fed from the outside is proper. For example, the redundant main word line is set to the select level on the basis of a chip select signal. As a result, the drive start timing of the redundant main word line is not delayed in the least from the drive start timing of the main word line. Thus, it is possible to prevent the event that the select drive timing of the redundant sub word line is delayed on account of the delay in the drive timing of the redundant main word line.

Semiconductor memory device having redundancy memory cells for replacing

A wide-bit output semiconductor storage device of high speed and low noise is provided in which output circuits are grouped into two groups and the two output circuit groups are so controlled as to be switched in directions of levels which are opposite to each other.

High speed, low noise semiconductor storage device

An MOS static type RAM has a memory cell array comprising of a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

MOS static type RAM having a variable load

An MOS static type RAM has a memory cell array comprising a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

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Hamura, Japan

Makoto Saeki