Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Hitachi Ulsi Engineering Corp.

Makoto Ogasawara

Hideo Aoki

Isamu Asano

Tsuyoshi Tamaru

Yoshinao Kawasaki

Masakazu Sagawa

Nobuo Owada

Osamu Tsuchiya

Toru Kaga

Fumio Ootsuka

Kazuyoshi Torii

Hiromichi Enami

Mitsuaki Horiuchi

Jun Sugiura

Osamu Kasahara

Hidetsugu Ogishi

Keisuke Funatsu

Masatoshi Tsuneoka

Takayoshi Kogano

Atsushi Wakahara

Hiroyuki Akimori

Sinichi Suzuki

Seiichirou Shirai

Tunehiko Tubone

Ken Tsugane

Nobuhiro Otsuka

Yoshihiro Ikeda

Tomotsugu Shimmyo

Hideo Miura

Hiroo Masuda

Jun Murata

Noriaki Okamoto

Masashi Horiguchi

Norio Hasegawa

Yoshitaka Tadaki

Makoto Ohkura

Aritoshi Sugimoto

Shinichi Fukada

Kiyonori Ohyu

Shinji Sakata

Yasunobu Tanizaki

Eiji Wakimoto

A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.

Method of designing a semiconductor device

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same

A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.

Method of fabricating low stress semiconductor devices with thermal oxide isolation

A field oxide film in a region where relief cells are formed is made wider than the field oxide film in a region where normal memory cells are formed thereby to make a field relaxation layer of the relief cells deeper than the field relaxation layer of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

Semiconductor integrated circuit device and process for manufacturing the same

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM

A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. In accordance with the manufacturing scheme, a semiconductor device produced includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.01 to 2.5 &mgr;m. In such a schemed device, a ratio of the width of the device region to the width of the device isolation region is from 2 to 50. Each device isolation region is a groove formed in the semiconductor substrate by etching a portion, among the pad oxide film formed on the surface of the semiconductor substrate and a nitride film formed on the pad oxide film, existing on the device isolation region, and having a depth of from 0 to 10 nm when measured from the position of the pad oxide film on the semiconductor substrate.

Low stress semiconductor devices with thermal oxide isolation

A field oxide film,in a region where relief cells are formed is made wider than the field oxide film,in a region where normal memory cells are formed thereby to make a field relaxation layer,of the relief cells deeper than the field relaxation layer,of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.

Semiconductor integrated circuit device, process for fabricating the

A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.

Semiconductor device having circuit element in stress gradient region by

Method of forming teos oxide and silicon nitride passivation layer on

Semiconductor integrated circuit device process for fabricating the same

Growing community of inventors

Ohme, Japan

Makoto Ogasawara