Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hitachi Ulsi Engineering Corp.

Elpida Memory, Inc.

Micron Technology Incorporated

Hitachi Hokkai Semiconductor Ltd.

Hitachi Vsli Engineering Corp.

Hiachi, Ltd.

Makoto Morino

Hiroshi Yoshioka

Shinji Udo

Sinichi Miyatake

Yasunori Yamaguchi

Mitsuhiro Takano

Manabu Tsunozaki

Kazuhiko Kajigaya

Masashi Horiguchi

Akira Endo

Ryoichi Hori

Takashi Yamazaki

Kazuyoshi Oshima

Kazuyuki Miyazawa

Jun Etoh

Yuji Sakai

Tetsurou Matsumoto

Yasuhiro Kasama

Shinichi Ikenaga

Eiji Miyamoto

Jiro Sawada

Hirokazu Saito

Atsushi Kumata

Shinichi Miyatake

Masaya Muranaka

Yukihide Suzuki

Kanehide Kenmizaki

Tetsuya Kitame

Kyoko Ishii

Yoshihisa Koyama

Hidetomo Aoyagi

Haitao Liu

Osamu Nagashima

Masayuki M Nakamura

Tsutomu Takahashi

Seiji Narui

Katsuyuki Sato

Shoji Kubono

Hitoshi Kawaguchi

Yosuke Yukawa

Shuichi Kubouchi

Shoji Wada

Masahiro Ogata

Fredrick David Fishburn

Kenji Mae

Masahiro Yoshida

Soichi Sugiura

Masahiro Katayama

Nobuhiko Ohno

Mark A Zaleski

Tetsuya Saeki

Koichi Nozaki

Oscar O Enomoto

Atsuko Otsuka

Akihiko Hoshida

Ichiro Abe

Yoshiyuki Nanjo

Jun Mitake

Terutaka Okada

Keisuke Hirofuji

Seiichi Shundo

A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.

Semiconductor devices including transistors comprising a charge trapping material, and related systems and methods

A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Semiconductor memory device and defect remedying method thereof

A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.

Boosted potential generation circuit and control method

A semiconductor integrated circuit device includes a memory array having first to Nth banks, where N is an integer greater than or equal to 2. The memory array further includes a redundancy block having first to Nth column recovery circuit blocks corresponding to the first to Nth banks, first to Nth row recovery circuit blocks corresponding to the first to Nth banks, first to Nth ECC fuse blocks corresponding to the first to Nth banks, and first to Nth ECC circuits corresponding to the first to Nth banks. During initial cycles, the first to Nth ECC circuits correct errors in column recovery fuse data in the first to Nth column recovery circuit blocks and errors in row recovery fuse data in the first to Nth row recovery circuit blocks by using ECC fuse data in the first to Nth ECC fuse blocks, respectively.

Redundancy semiconductor memory device with error correction code (ECC) circuits for correcting errors in recovery fuse data

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit

Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

Semiconductor memory device and memory system

Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Growing community of inventors

Akishima, Japan

Makoto Morino