Mitsubishi Denki Kabushiki Kaisha

Other

Mako Kobayashi

Fukashi Morishita

Akira Yamazaki

Yasuhiko Taito

Mihoko Akiyama

Nobuyuki Fujii

Kazutami Arimoto

Takahiro Tsuruda

Takeshi Fujino

Mitsuya Kinoshita

Tetsushi Tanizaki

Teruhiko Amano

With power-on detection circuits provided for a plurality of power supply voltages, a main power-on detection signal is maintained at the active state to reset an internal node while at least one of the power-on detection signals is active. In a multi-power semiconductor integrated circuit device, current consumption at the time of power-up is reduced.

Multi-power semiconductor integrated circuit device

Oscillation outputs which are different for respective detector signals output from a first detector circuit and a second detector circuit, are obtained from a first ring oscillator and a second ring oscillator respectively corresponding to the detector circuits. A selector selects and outputs one of the oscillation outputs. Accordingly, it is sufficient to provide only one pump circuit in a circuit producing a substrate bias voltage.

Substrate bias voltage generating circuit

When a tuning mode signal VTUNE is activated, control clock signal TCLK is output, and counter counts up tuning signals TSIG to TSIG . Tuning circuits render conductive the terminals of respective transistors, and reference potential Vref lowers in accordance with the reduction in the resistance value. When reference potential Vref attains equal to the external reference potential Ext.Vref, differential amplifier circuit stops output of the control clock signal TCLK. In accordance with the plurality of the determined tuning signals TSIG to TSIG , fuse elements inside the tuning circuits are programmed.

Semiconductor device including internal potential generating circuit allowing tuning in short period of time and reduction of chip area

In a VDC circuit, a differential amplifier compares a first reference potential with an internal supply potential to generate a control signal according to a result of the comparison. A constant current source transistor receives at its gate a second reference potential supplied through a path different from that of the first reference potential to operate for controlling an operation current value of the differential amplifier. A drive transistor changes conductance between a node for outputting the internal supply potential and a supply potential according to the control signal.

Voltage downconverter circuit capable of reducing current consumption while keeping response rate

A plurality of pump modules are provided, the number of pump modules to be activated is changed depending on a mode of operation, and the number of pump modules to be activated is also adjusted with the specification of interest taken into consideration. There can be provided an internal voltage generation circuit occupying a small area and readily capable of accommodating a change in specification.

Internal voltage generation circuit

A semiconductor integrated circuit device includes a reference voltage generating circuit that can be tuned without a circuit replacement when a process condition is varied. The reference voltage generating circuit is constituted such that two different circuit configurations having different temperature properties are switched by a first switch. In each of the circuit configurations, a switch control circuit in which tuning can be performed by switching a second switch generates a control signal based on a test mode and supplies the signal to the first switch for tuning. Thereafter, a fuse in the switch control circuit is blown off to generate a control signal, and reference voltage Vref is output.

Semiconductor integrated circuit device having circuit generating reference voltage

A semiconductor device includes a constant voltage generation circuit generating a constant voltage commonly to reference voltages corresponding to a plurality of internal voltages. The plurality of reference voltages are generated from the common constant voltage. Thus, the semiconductor device for generating internal voltages is implemented, which allows reduction in layout area and decrease in test time for voltage adjustment.

Semiconductor integrated circuit device capable of stably generating internal voltage independent of an external power supply voltage

In a control voltage generating section for supplying a control voltage to a gate of a charge transfer gate for transferring charges received from a capacitor to an output node to generate an internal voltage, the amplitude of the control voltage is switched in accordance with a switch signal. An internal voltage generating circuit making it possible to improve design efficiency, reliability and yield and reduce power consumption is provided.

Semiconductor device capable of generating internal voltage effectively

A voltage generation circuit includes a digital type VDC. The digital VDC includes a differential amplify circuit amplifying a voltage deviation of a reference voltage signal from a detection voltage signal to output the amplified voltage to a control node, a signal conversion circuit providing either an H level or an L level according to the voltage level of the control node, and an output transistor connecting an external power supply line and an internal power supply voltage node according to an output voltage of the signal conversion circuit. The center of the range of the varying voltage level of the control node is set by shifting to the logic threshold value of the signal conversion circuit.

Constant internal voltage generation circuit

A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.

Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area

The voltage converting circuit,includes a standby VDC, an active VDC which operates when the semiconductor integrated circuit device is activated and has current drivability larger than that of standby VDC, and a drivability control circuit. Drivability control circuit generates a control signal in accordance with operational frequency of the semiconductor integrated circuit device. Current drivability of the active the VDC is controlled in accordance with the operational frequency by the control signal.

Voltage converting circuit allowing control of current drivability in accordance with operational frequency

When a tuning mode signal VTUNE is activated, control clock signal TCLK is output, and counter counts up tuning signals TSIG,to TSIG,. Tuning circuits render conductive the terminals of respective transistors, and reference potential Vref lowers in accordance with the reduction in the resistance value. When reference potential Vref attains equal to the external reference potential Ext.Vref, differential amplifier circuit stops output of the control clock signal TCLK In accordance with the plurality of the determined tuning signals TSIG,to TSIG,, fuse elements inside the tuning circuits are programmed.

Semiconductor device including voltage down converter allowing tuning in short period of time and reduction of chip area

A semiconductor integrated circuit device includes an oscillator generating a clock signal and a charge pump circuit. The charge pump circuit includes capacity elements and an output transistor. The capacity element boosts a voltage on a boost node. The transistor (clamp circuit) clamps the voltage level on the boost node to a constant value. The capacity element controls the gate voltage of the output transistor. The clamp circuit is used to suppress a voltage applied to the transistors and the MOS capacity element, and suppresses generation of hot carriers.

Substrate voltage generating circuit provided with a transistor having a thin gate oxide film and a semiconductor integrated circuit device provided with the same

A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

Semiconductor memory device

A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.

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Hyogo, Japan

Mako Kobayashi