Intel Corporation

Honeywell International Inc.

Tokyo Ohka Kogyo Co., Ltd.

Makarem A Hussein

Sam Sivakumar

Peter K Moon

Valery M Dubin

Boyan Boyanov

Ebrahim Andideh

Ruth Amy Brain

Daniel C Diana

Alan M Myers

Michael D Goodner

Kevin J Lee

Victor Y Lu

Bo Li

Nancy E Iwamoto

Roger Leung

Joseph T Kennedy

Chin-Chang Cheng

Lawrence N Brigham

Phi L Nguyen

Raymond E Cotner

Angelo Kandas

Mark A Fradkin

Charles H Recchia

Mark T Bohr

Gregory Martin Chrysler

Kevin O'Brien

Saikumar Jayaraman

Paul A Koning

Kazumasa Wakiya

Jun He

Takayuki Haraguchi

Rick M Davis

Shigeru Yokoi

Shan Christopher Clark

Lana Jong

Magdy S Abdelrahman

Jim Powers

Robert Turklot

Joseph Honeywell International Inc Kennedy

Bo Honeywell International Inc Li

Nancy Honeywell International Inc Iwamoto

Victor Honeywell International Inc Lu

Roger Honeywell International Inc Leung

Kazumasa c/o Tokyo Ohka Kogyo Co Ltd Wakiya

Lana I Jong

Shigeru c/o Tokyo Ohka Kogyo Co Ltd Yokoi

Takayuki c/o Tokyo Ohka Kogyo Co Ltd Haraguchi

An absorbing composition is described herein that includes at least one inorganic-based compound, at least one absorbing compound, and at least one material modification agent. In addition, methods of making an absorbing composition are also described that includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, an acid/water mixture, and one or more solvents to form a reaction mixture; and b) allowing the reaction mixture to form the absorbing composition at room temperature. Another method of making an absorbing composition includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, an acid/water mixture, and one or more solvents to form a reaction mixture; and b) heating the reaction mixture to form the absorbing composition. Yet another method of making an absorbing composition is described that includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, and one or more solvents to form a reaction mixture, wherein the at least one material modification agent comprises at least one acid and water; and b) heating the reaction mixture to form an absorbing material, a coating or a film. In other methods of making an absorbing composition described herein, those methods include: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, and one or more solvents to form a reaction mixture, wherein the at least one material modification agent comprises at least one acid and water; and b) allowing the reaction mixture to form an absorbing material, a coating or a film.

Antireflective coatings for via fill and photolithography applications and methods of preparation thereof

A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land.

Dielectric spacers for metal interconnects and method to form the same

An absorbing composition is described herein that includes at least one inorganic-based compound, at least one absorbing compound, and at least one material modification agent. In addition, methods of making an absorbing composition are also described that includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, and one or more solvents to form a reaction mixture, wherein the at least one material modification agent comprises at least one acid and water; and b) heating the reaction mixture to form an absorbing material, a coating or a film.

Described herein are embodiments of a method that includes forming a hard mask over an interlayer dielectric layer, patterning said hard mask, etching said interlayer dielectric layer, and removing said hard mask during a post-etch clean with a wet etchant having a selectivity to etch said hard mask at a greater rate than said interlayer dielectric layer.

Soluble hard mask for interlayer dielectric patterning

A cleaning composition comprises at least quaternary ammonium hydroxide, a water-soluble organic solvent, water, an anticorrosive, and potassium hydroxide of 1 mass percent or less of a total amount of the solution. This cleaning composition can singly and effectively remove a photoresist film, a buried material, a metallic residue from the surface of a semiconductor substrate.

Cleaning composition and method of cleaning semiconductor substrate

Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Methods and apparatuses for producing a polymer memory device

A method of forming an interconnection that includes introducing a barrier material in a via of a dielectric to a circuit device on a substrate in such a manner to deposit the barrier material on the circuit device, introducing a seed material into the via in manner that leaves the barrier material overlying the circuit device substantially exposed, substantially removing the barrier material overlying the circuit device, and introducing a conductive material into the via to form the interconnection.

Continuous metal interconnects

A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure.

Damascene process for fabricating interconnect layers in an integrated circuit

In some embodiments, the invention provides a stress mitigation layer that reduces stress in a layer of a microelectronic device that is below a conductive connection structure, such as a bump.

Stress mitigation layer to reduce under bump stress concentration

Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures

Apparatus and methods in accordance with the present invention utilize thermoelectric cooling (TEC) technology to provide enhanced power distribution and/or dissipation from a microelectronic die and/or microelectronic packages. Individual TEC devices are thermally interconnected with the microelectronic die in a number of placement configurations, including between the microelectronic die and the heat sink, on the integrated heat spreader (IHS) inner surface, and on the IHS outer surface. TEC devices comprise p- and n-type semiconducting material created using similar process as the microcircuits. The TEC devices are located in various regions within or on the microelectronic die, including directly below the microcircuits, on the backside of the microelectronic die, and on a separate substrate of microelectronic die material fabricated apart from the microelectronic die and subsequently thermally coupled to the backside of the microelectronic die.

Thermoelectric cooling for microelectronic packages and dice

Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs

Growing community of inventors

Beaverton, OR, United States of America

Makarem A Hussein