International Business Machines Corporation

Advanced Technology Materials, Inc.

Zeon Corporation

Shipley Company, L.l.c. of Marlborough

Mahmoud M Khojasteh

Pushkara Rao Varanasi

Wu-Song S Huang

George Gabriel Totir

Ali Afzali-Ardakani

Kuang-Jung Chen

Ahmad D Katnani

Alexander Reznicek

Pouya Hashemi

Ratnam Sooriyakumaran

Ranee W Kwong

Margaret C Lawson

William R Brunsvold

Ronald Wayne Nunes

Kaushal S Patel

Qinghuang Lin

Robert David Allen

Sebastian Ulrich Engelmann

Tak H Ning

John Anthony Fitzsimmons

Emanuel Israel Cooper

Robert L Bruce

Phillip Joe Brock

Nicholas C M Fuller

Wenjie Li

Jennifer V Muncy

Ronald Anthony DellaGuardia

Sarah Jane Vella

Takashi Ando

Masahiro Nakamura

Yu Zhu

Eric Andrew Joseph

Dario Leonardo Goldfarb

Sean David Burns

David Robert Medeiros

Satyavolu S Papa Rao

Rajiv M Ranade

Ranee Wai-Ling Kwong

Irene Popova

George J Hefferon

Pratik P Joshi

Nageshwer Rao Bantu

Dominic Changwon Yang

Bang N To

Timothy M Hughes

Vishal Chhabra

Tricia Breen Carmichael

Karthik Balakrishnan

Kevin K Chan

Laertis Economikos

Dirk Pfeiffer

Deborah A Neumayer

Willi Volksen

Jeffrey Curtis Hedrick

Krishna Gandhi Sachdev

Roger F Sinta

Hsinyu Tsai

Hongwen Yan

Hoa D Truong

Michael B Korzenski

Frances Anne Houle

Harbans S Sachdev

Young-Hee Kim

Karl E Boggs

George W Orsula

Wei-Tsu Tseng

Marinus Hopstaken

Tricia Lynn Breen

Adam D Ticknor

Donald Clifford Hofer

John M Papalia

Elwood Herbert Macy

James Hannah

Anthony F Arnold

James J Steffes

Masahiro Yamazaki

Uday Kumar

Prabodh R Shah

Ying Ying Cheng

Renjie Zhou

Quighuang Lin

Vamsi Devarapalli

Colin J Goyette

James I Fahey

Richard D Diller, Deceased

Michael R Kennett

Patricia M Cotts

Michael W Owens

James L Simpson

Julie Cissell

A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

III-V lateral bipolar junction transistor on local facetted buried oxide layer

A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.

Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation

A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating dielectric.

Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques

A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.

Plasma shallow doping and wet removal of depth control cap

A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH)(NO)),(CAN).

[object Object]

A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained.

Neutral hard mask and its application to graphoepitaxy-based directed self-assembly (DSA) patterning

Cleaning solutions and processes for cleaning semiconductor devices or semiconductor tooling during manufacture thereof generally include contacting the semiconductor devices or semiconductor tooling with an acidic aqueous cleaning solution free of a fluorine containing compound, the acidic aqueous cleaning solution including at least one antioxidant and at least one non-oxidizing acid.

Cleaning composition and process for cleaning semiconductor devices and/or tooling during manufacturing thereof

A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module.

Post metal chemical-mechanical planarization cleaning process

Cleaning processes for cleaning semiconductor devices or semiconductor tooling during manufacture thereof generally include contacting the semiconductor devices or semiconductor tooling with an antioxidant to form an insoluble adduct followed by solubilizing the adduct with a basic aqueous cleaning solution.

Process for cleaning semiconductor devices and/or tooling during manufacturing thereof

An aqueous solution of a cerium (IV) complex or salt having an extended lifetime is provided. In one embodiment, the extended lifetime is achieved by adding at least one booster additive to an aqueous solution of the cerium (IV) complex or salt. In another embodiment, the extended lifetime is achieved by providing an aqueous solution of a cerium (IV) complex or salt and a cerium (III) complex or salt. The cerium (III) complex or salt can be added or it can be generated in-situ by introducing a reducing agent into the aqueous solution of the cerium (IV) complex or salt. The aqueous solution can be used to remove a mask material, especially an ion implanted and patterned photoresist, from a surface of a semiconductor substrate.

Aqueous cerium-containing solution having an extended bath lifetime for removing mask material

A method of rendering a substrate catalytic to electroless metal deposition comprising the steps of: (a) depositing a ligating chemical agent on the substrate, which is capable of both binding to the substrate and ligating to an electroless plating catalyst; and (b) ligating the electroless plating catalyst to the ligating chemical agent, wherein the ligating chemical agent has the chemical structure: 

Materials and methods for immobilization of catalysts on surfaces and for selective electroless metallization

Growing community of inventors

Poughkeepsie, NY, United States of America

Mahmoud M Khojasteh