Intel Corporation

Other

Mahesh S Natu

Shamanna M Datta

Mohan J Kumar

Murugasamy K Nachimuthu

Vincent J Zimmer

Rahul Khanna

Robert Charles Swanson

Michael A Rothman

Frank Binns

Altug Koker

Balaji Vembu

Murali Ramadoss

Ankur N Shah

Aditya Navale

David M Puffer

Jiewen Yao

Andrew J Fish

Rajesh S Parthasarathy

Bryan R White

Eric Dahlen

Gautam Doshi

Anil S Keshavamurthy

Sham M Datta

Robert Patrick Hale

Anand K Enamandram

Vivekananthan Sanjeepan

Mohan Nair

Yan Li

Muthukumar Swaminathan

Baskaran Ganesan

Thanunathan Rangarajan

Rajesh Nagaraja Murthy

David J Harriman

Narayan Ranganathan

Swadesh Choudhary

John V Lovelace

Malay Trivedi

James R Vash

Alberto J Munoz

Qin Long

Xiaoyu Ruan

Robert A Branch

Manjula Peddireddy

Scott T Durrant

Liang Cui

Kerry Vander Kamp

Scott W Kirvan

Debendra Das Sharma

Siddhartha Chhabra

Hormuzd M Khosravi

Wei P Chen

Mahesh U Wagh

Mark A Schmisseur

Sarathy Jayakumar

Sivakumar Radhakrishnan

Adrian R Pearson

Mallik Bulusu

Stephen S Pawlowski

Bill Nale

Robert J Safranek

Tessil Thomas

Richard Paul Mangold

Lakshminarayana Pappu

Kirk D Brannock

Vedaraman Geetha

Sailesh Kottapalli

Madhusudhan Rangarajan

Allen Jay Baum

Purushottam Goel

Jing Ling

Bharat S Pillilli

Dimitrios Ziakas

Luke L Chang

Michael Berger

Zhenyu Zhu

Scott P Bobholz

Ramadass Nagarajan

James Earl McCormick, Jr

Lakshmipriya Seshan

Alberto J Martinez

Andy M Rudoff

Robert W Cone

Rajesh P Banginwar

Mukesh Kataria

Jeff Wiedemeier

Russell J Wunderlich

Narasimha Lanka

Nitish Paliwal

Erik A McShane

Michelle M Sebot

Barry Kennedy

Babak B Nikjou

C Brendan Traw

Peeyush Purohit

John P Lambino

Tiffany J Kasanicky

John R Lindsley

Miles F Schwartz

Jayasekhar Tholiyil

Chris Ruffin

In one embodiment, a device includes: an interface circuit to couple the device to a host via a link, where in a first mode the interface circuit is to be configured as an integrated switch controller and in a second mode the interface circuit is to be configured as a link controller; and a fabric coupled to the interface circuit, the fabric to couple to a plurality of hardware circuits, where the fabric is to be dynamically configured for one of the first mode or the second mode based on link training of the link. Other embodiments are described and claimed.

System, method, apparatus and architecture for dynamically configuring device fabrics

In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.

System, apparatus and method for handling multi-protocol traffic in data link layer circuitry

Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express—PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.

Exposing cryptographic measurements of peripheral component interconnect express (PCIE) device controller firmware

A cache flush request is received in a first phase of a persistent memory flush flow, where the first phase is initiated by a host processor, and the cache flush request requests that data in cache memory be flushed to persistent memory within a system. A cache flush response is sent in the first phase responsive to the cache flush request, where the cache flush response identifies whether an error is detected in the first phase. A memory buffer flush request is received in a second phase of the persistent memory flush flow, where the second phase is initiated by the host processor upon completion of the first phase, and the memory buffer flush request requests that data in buffers of persistent memory devices in the system be flushed to persistent memory. A memory buffer flush response is sent in the second phase responsive to the memory buffer flush response.

Global persistent flush

A port is to couple to another die over a die-to-die (D2D) link and includes a die-to-die (D2D) adapter to determine, from a set of registers, a set of capabilities of the D2D adapter to advertise in a negotiation with a link partner D2D adapter, where the D2D adapter is on a die and the link partner D2D adapter is located on a remote link partner die. A first capabilities advertisement message is sent to the link partner D2D adapter to advertise the set of capabilities to the link partner D2D adapter. A second capabilities advertisement message is received from the link partner D2D adapter, wherein the second capabilities advertisement message identifies a set of capabilities of the link partner D2D adapter. A final configuration of a D2D link is determined to couple the die to the link partner die.

Parameter exchange for a die-to-die interconnect

Various embodiments provide apparatuses, systems, and methods for establishing, by a data object exchange (DOE entity) of a peripheral component interconnect express (PCIe) device, a first session for communication between a first host entity of a host device and a first PCIe entity of the PCIe device, and a second session for communication between a second host entity of the host device and a second PCIe entity of the PCIe device. The first session may have a first security policy and be a session of a first connection between the PCIe device and the host device. The second session may have a second security policy and be a session of a second connection between the PCIe device and the host device. Other embodiments may be described and claimed.

Support of PCIe device with multiple security policies

Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Circuitry and methods for spatially unique and location independent persistent memory encryption

A system or a device can include a processor core comprising one or more hardware processors; a processor memory to cache data; a memory link interface to couple the processor core with one or more attached memory units; and a platform firmware to determine that a device is connected to the processor core across the memory link interface; determine that the device comprises an attached memory; determine a range of at least a portion of the attached memory available for the processor core; map the range of the portion of the attached memory to the processor memory; and wherein the processor core is to use the range of the portion of the attached memory and the processor memory to cache data.

Host-managed coherent device memory

Apparatuses, methods, and computer-readable media are provided for operating a port manager to detect a first link condition or a second link condition of a circuitry. Under the first link condition, a first link between a downstream port of the circuitry and an upstream port of a switch is compatible to a first protocol, and a second link between a downstream port of the switch and an upstream port of a device is compatible to the second protocol. Under the second link condition, the first link exists and is compatible to the first protocol, while there is no second link being compatible to the second protocol. The port manager is to operate the downstream port of the circuitry according to the second protocol on detection of the first link condition, or according to the first protocol on detection of the second link condition. Other embodiments may be described and/or claimed.

Mechanism for device interoperability of switches in computer buses

An apparatus comprising a computer platform, including a central processing unit (CPU) comprising a first security engine to perform security operations at the CPU and a chipset comprising a second security engine to perform security operations at the chipset, wherein the first security engine and the second security engine establish a secure channel session between the CPU and the chipset to secure data transmitted between the CPU and the chipset.

Platform security mechanism

Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

Apparatus and method for scalable error detection and reporting

Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express&#x2014;PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.

Exposing cryptographic measurements of peripheral component interconnect express (PCIe) device controller firmware

Control logic and methods to map host-managed device memory to a system address space

Growing community of inventors

Folsom, CA, United States of America

Mahesh S Natu