Intel Corporation

Nvidia Corporation

Magnus Andersson

Tomas G Akenine-Moller

Jon N Hasselgren

John Matthew Burgess

Robert M Toth

Gregory Muthler

Carl Jacob Munkberg

Jim K Nilsson

Bjorn Johnsson

Henry Packard Moreton

Yury Y Uralsky

Ian Kwong

Edward Biddulph

Tomas Guy Akenine-Möller

Marco Salvi

Franz Petrik Clarberg

Christoph Kubisch

Nikhil Dixit

James Robertson

Timo Tapani Viitanen

Jim Kjell David Nilsson

Björn Johnsson

Levi Oliver

Johannes Deligiannis

Thomas G Akenine-MÖLLER

Carl J Munkberg

Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced round-trip communications with a processor are disclosed. The reduction of round-trip communications with a processor during traversal is achieved by having a visibility mask that defines visibility states for regions within a geometric primitive available to be accessed in the ray tracing hardware accelerator when a ray intersection is detected for the geometric primitive.

Accelerating triangle visibility tests for real-time ray tracing

A Displaced Micro-mesh (DMM) primitive enables high complexity geometry for ray and path tracing while minimizing the associated builder costs and preserving high efficiency. A structured, hierarchical representation implicitly encodes vertex positions of a triangle micro-mesh based on a barycentric grid, and enables microvertex displacements to be encoded efficiently (e.g., as scalars linearly interpolated between minimum and maximum triangle surfaces). The resulting displaced micro-mesh primitive provides a highly compressed representation of a potentially vast number of displaced microtriangles that can be stored in a small amount of space. Improvements in ray tracing hardware permit automatic processing of such primitive for ray-geometry intersection testing by ray tracing circuits without requiring intermediate reporting to a shader.

Displaced micro-meshes for ray and path tracing

Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.

Reducing false positive ray traversal in a bounding volume hierarchy

Reducing false positive ray traversal using point degenerate culling

An alternate root tree or graph structure for ray and path tracing enables dynamic instancing build time decisions to split any number of geometry acceleration structures in a manner that is developer transparent, nearly memory storage neutral, and traversal efficient. The resulting traversals only need to partially traverse the acceleration structure, which improves efficiency. One example use reduces the number of false positive instance acceleration structure to geometry acceleration structure transitions for many spatially separated instances of the same geometry.

Generation and traversal of partial acceleration structures for ray tracing

Reducing false positive ray traversal using ray clipping

Enhanced techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure are disclosed. The traversal efficiency of such hardware accelerators are improved, for example, by transforming a ray, in hardware, from the ray's coordinate space to two or more coordinate spaces at respective points in traversing the hierarchical acceleration structure. In one example, the hardware accelerator is configured to transform a ray, received from a processor, from the world space to at least one alternate world space and then to an object space in hardware before a corresponding ray-primitive intersection results are returned to the processor. The techniques disclosed herein facilitate the use of additional coordinate spaces to orient acceleration structures in a manner that more efficiently approximate the space occupied by the underlying primitives being ray-traced.

Ray tracing hardware acceleration with alternative world space transforms

Embodiments described herein enable a hierarchical-Z unit of a graphics processor to be primed using Hi-Z data generated by occlusion culling operations performed on a general purpose processor. One embodiment provides for instructions to cause operations including performing occlusion culling for a scene via the general purpose processor and storing generated hierarchical-Z data. The Hierarchical-Z data generated during the occlusion culling operations can be shared with the graphics processor and used to prime a hierarchical-Z unit of the graphics processor. The at least a portion of the scene can then be rendered using the hierarchical-Z data after priming the hierarchical-Z unit, improving the effectiveness of hierarchical-Z operations of the graphics processor for the scene.

Priming hierarchical depth logic within a graphics processor

A texture level of detail (LOD) approximation may be performed utilizing ray differentials and a G-buffer. For example, a scene to be rendered is identified, and a G-buffer of the scene is rendered. Additionally, ray tracing is started for the scene, and during the ray tracing, a ray differential is created by accessing the G-buffer. Further, the created ray differential is appended to a current ray, and the created ray differential is traced.

Creating a ray differential by accessing a G-buffer

Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimization for texture-dependent discard operations are described. In an embodiment, a processor performs one or more operations (such as HiZ or Hierarchical Stencil test) on depth data of an image tile in response to a determination that texture space bounds of the image tile is fully opaque. The processor performs the one or more operations regardless of whether a discard operation is enabled. Other embodiments are also disclosed and claimed.

Hierarchical Z-culling (HiZ) optimization for texture-dependent discard operations

In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.

Reducing power consumption during graphics rendering

A method, computer readable medium, and system are disclosed for performing a texture level-of-detail approximation. The method includes the steps of identifying a scene to be rendered, projecting a ray passing through a pixel of a screen space, resulting in a first hit point at a geometry element within the scene, determining a footprint angle of the pixel, determining a curvature measure for the geometry element at the first hit point within the scene, computing a texture level of detail (LOD) approximation for a component of the scene, utilizing the footprint angle of the pixel and the curvature measure for the geometry element, and performing, utilizing a hardware processor, one or more rendering operations for the scene, utilizing the texture LOD approximation.

Performing a texture level-of-detail approximation

An apparatus and method are described for performing an efficient depth prepass. For example, one embodiment of a method comprising: a method comprising: performing a first pass through a specified portion of a graphics pipeline with only depth rendering active; initializing a coarse depth buffer within the specified portion of the graphics pipeline during the first pass, the coarse depth buffer storing depth data at a level of granularity less than that stored in a per-pixel depth buffer, which is not initialized during the first pass; and performing a second pass through the graphics pipeline following the first pass, the second pass utilizing the full graphics pipeline and using values in the coarse depth buffer initialized by the first pass.

Method and apparatus for efficient depth prepass

An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.

Growing community of inventors

Helsingborg, Sweden

Magnus Andersson