Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (Corporation)

Other

Luona Goh

Simon Yew-Meng Chooi

Wei Lu

Siew Lok Toh

Shyue Seng Tan

Elgin Kiok Quek

Huang Liu

Liang Choo Hsia

Jae Gon Lee

Fan Zhang

Tae Jong Lee

Huey Ming Chong

Xiaomei Bu

Kho Liep Chok

Yee Mei Foong

Chian Yuh Sin

Jeff Shu

Meng Luo

Tong Earn Tay

Jingze Tian

A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.

Stress liner for stress engineering

A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolation region in the substrate. A transistor is also formed in the active region and a pre-metal dielectric layer formed over the substrate and transistor. At least one of the dielectric layer in isolation region or the pre-metal dielectric layer includes a stressed OTEOS oxide having a stress retaining dopant, wherein the concentration of the stress retaining dopant is sufficient to retard stress degradation of the OTEOS oxide.

Integrated circuit including a stressed dielectric layer with stable stress

A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

Integrated circuit with protective moat

Method of improving adhesion of low dielectric constant films to other dielectric films and barrier metals in a damascene process are achieved. In one method, a low dielectric constant material layer is deposited on a substrate. Silicon ions are implanted into the low dielectric constant material layer. Thereafter, a TEOS-based silicon oxide layer is deposited overlying the low dielectric constant material whereby there is good adhesion between low dielectric constant material layer and the TEOS-based silicon oxide layer. In another method, a low dielectric constant material layer is deposited on a substrate. A silicon-based dielectric layer is deposited overlying the low dielectric constant material wherein the silicon-based dielectric layer is not silicon oxide whereby there is good adhesion between the low dielectric constant material layer and the silicon-based dielectric layer.

Method to improve adhesion of dielectric films in damascene interconnects

Growing community of inventors

Singapore, Singapore

Luona Goh