Intel Corporation

Luke J Garner

Peng T Li

Cheng Xu

Andrew James Brown

Chong Zhang

Ying Wang

Lauren Ashley Link

Bin Zou

John J Beatty

Hemanth K Dhavaleswarapu

Liwei Cheng

Marco Aurelio Cartas Ayala

Dinesh Padmanabhan Ramalekshmi Thanu

Venkata Suresh Guthikonda

Yonghao An

Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.

Vias for package substrates

Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.

Semiconductor package having sealant bridge

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Chandler, AZ, United States of America

Luke J Garner