Standard Microsystems Corporation

Freescale Semiconductor,inc.

Qualcomm Incorporated

Motorola Corporation

Qualcomm Technologies International, Ltd.

Luis Briones

Klaas Wortel

Troy L Stockstad

Noshir Behli Dubash

David K Lovelace

Brandt Braswell

Chuanzhao Yu

Kuor-Hsin Chang

Jeffrey Koeller

Clinton Powell

Karl J Huehne

Jeff Koeller

Michael Schödel

Charles Matsumoto

A method for low power communication links between wireless devices is described. The method includes establishing, by a first wireless device, a first magnetic communication link to a source wireless device through a human body. The method also includes establishing, by a second wireless device, a second magnetic communication link to the source wireless device through the human body. The method also includes receiving, by the first wireless device via the first magnetic communication link and the second wireless device via the second magnetic communication link, communications from the source wireless device through the human body.

Low power communication links between wireless devices

Tuners, multi-tuner receivers and methods of configuring multiple tuners are provided. A tuner on an integrated circuit includes an RF amplifier configured to be coupled to an antenna to amplify an RF signal received from the antenna, a bidirectional port configured to be coupled to another tuner and a bidirectional port circuit coupled between the RF amplifier and the bidirectional port. The bidirectional port circuit includes signal routing circuitry and a programmable control that is configured to control the signal routing circuitry to implement one of an input port, an output port or a disabled port.

Bidirectional ports for multi-tuner background radios

A continuous time sigma delta analog to digital converter is provided. The continuous time sigma delta analog to digital converter may include, but is not limited to, an analog to digital converter having a feedback loop, and a feedback loop controller coupled to the analog to digital converter, the feedback loop controller configured to adjust delay in the feedback loop by controlling a variable delay component in the feedback loop.

Delay compensated continuous time sigma delta analog-to-digital converter

Apparatus for voltage regulation circuits and related operating methods are provided. An exemplary voltage regulation circuit includes a voltage regulation arrangement that provides a regulated output voltage based on an input voltage reference, a phase compensation arrangement coupled to the voltage regulation arrangement and configured to increase a phase margin of the voltage regulation arrangement, and detection circuitry coupled to the phase compensation arrangement. The detection circuitry is configured to disable the phase compensation arrangement in response to detecting an output current that is less than a threshold value.

Voltage regulation circuitry and related operating methods

In a wireless 802.15.4 communication system, a method and system are provided for switching between a predetermined protocol transmission mode and a high-speed transmission mode by including signaling mode information in a data packet () to instruct the receiver device () to demodulate at least a data payload using the predetermined transmission mode if the signaling mode information comprises a first predetermined value, and to demodulate at least the data payload using the high-speed transmission mode if the signaling mode information comprises a second predetermined value. The signaling mode information may be included in the SFD field of an 802.15.4 SHR structure to instruct the receiver how to demodulate or process the data packet, or may be included as desired anywhere in the data packet to instruct the receiver how to demodulate or process one or more subsequent data packets.

Initiation of high speed overlay mode for burst data and real time streaming (audio) applications

A linear, half-rate clock and data recovery (CDR) circuit for recovering clock information embedded in a received data signal. The half-rate CDR circuit comprises a phase detector that may receive the data signal and generate a phase error signal representative of the phase difference between the received data signal and a clock signal produced by a voltage-controlled oscillator (VCO) of the CDR circuit. The half-rate CDR typically changes the frequency of the clock signal and generates a clock signal that is aligned with the baud center of the received data signal. More specifically, when the half-rate CDR circuit is in a locked condition, both the rising and falling edges of the clock signal are aligned with the baud center of the received data signal. The half-rate CDR preferably generates a clock signal with an average frequency that is half the data rate of a received data signal.

Linear half-rate clock and data recovery (CDR) circuit

A current-mode direct conversion RF receiver is presented. In one set of embodiments the RF receiver comprises a simple transconductor input stage to create a current-mode modulated signal from a voltage-mode modulated signal. A downconversion mixer may be coupled to the transconductor input stage via a low impedance current cascode stage, and may operate to create a set of current-mode quadrature baseband signals from the current-mode modulated signal. The downconversion mixer may be implemented with a transistor-switching network, which may be driven by a phase locked loop (PLL) with quadrature outputs. The set of current-mode quadrature baseband signals may be converted back to the voltage domain by a transimpedance filter, which may perform channel selection for the receiver. The transimpedance filter may additionally include a low frequency zero to remove DC offsets. The receiver may be implemented using CMOS design technologies and operated with minimal self-mixing effects, minimal DC offset in the baseband signal, and utilizing low voltages.

Current-mode direct conversion receiver

Detecting a radio frequency (RF) environment around a computer and using a power management scheme for an RF user input device being used by the computer system. If the computer system is in a single user environment, a power management scheme may be used to conserve power on the RF user input device. If the computer system is in a multi-user environment, a power management scheme may be used to minimize interference between neighboring computer systems by minimizing the signal strength of the RF signal from the RF user input device and the RF signal from the computer system.

Selective implementation of power management schemes based on detected computer operating environment

A radio transmitter system designed using an FSK modulator with IQ up-mixers and sinewave coded digital-to-analog converters (DACs). The radio transmitter system may include a frequency shift keying (FSK) coding logic circuit coupled to the inputs of an IQ modulation and image reject up-mixer through a respective DAC and a respective low pass filter (LPF) for each the I and the Q channels. The FSK modulation scheme may employ sine and cosine signals for the I and Q channels, respectively, where the sine and cosine waves are directly coded into the DACs. The coded levels required by the DACs may be generated using current sources and may be Gray-coded. The output of the IQ modulation and image reject up-mixer may be connected to a power amplifier, which may be used to transmit the modulated RF signal via a loop antenna.

FSK modulator using IQ up-mixers and sinewave coded DACs

In one set of embodiments, the invention comprises a system and method for automatically trimming the center frequency of a VCO in a PLL. The trimming may be performed by a digitally controlled trimming circuit, which may be operated to modify a gain of the VCO and may be used as part of a clock recovery architecture or as part of a high-end PLL. It may also be used by itself in low-end PLLs. In one embodiment, a second loop based solely on the frequency difference between a reference frequency and a divided output frequency of the VCO is introduced into the PLL loop. This frequency loop may be optimized by the inclusion of a gain control stage, which may lower the locking time. A control module may also be introduced to delay the deployment of the phase detector until the frequency loop has fully converged, that is until trimming has been completed, thus preventing the two loops from interfering with each other and compromising each other's performance.

All digital PLL trimming circuit

A low-power phase detector with differential output may comprise a control signal generator. In one embodiment, two cyclic waveforms whose phase relationship is to be measured may be input to a control signal generator. The control signal generator may output a first control signal corresponding to the first cyclic waveform such that the control signal is de-asserted at a specific point with respect to the first cyclic waveform. For example, the control signal may be de-asserted corresponding to the rising edge of the first cyclic waveform. The control signal generator may also output a second control signal corresponding to the second cyclic waveform such that the control signal is asserted at a specific point with respect to the second cyclic waveform. For example, the control signal may be asserted corresponding to the falling edge of the second cyclic waveform.

Phase detector for low power applications

A PLL system ( ) includes a clock sequence generator ( ). Clock sequence generator ( ) provides a clock that steps down from a fast frequency through several steps to a frequency of zero. This step-down non-linear digression of frequencies causes a counter ( ) driving a tank circuit of a self-calibrating VCO to achieve lock at an extremely rapid rate. The PFD ( ) generates an analog signal based on the phase and frequency relationship of the reference and feedback clock signals. The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit ( ) and the signals UP and DOWN are supplied to the counter ( ). The counter ( ) provides a count value that controls the resonant frequency generated by the tank circuit. The convergence speed of the PLL system ( ) is accelerated by the effects of the step-down clock provided by the clock sequence generator ( ).

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Chandler, AZ, United States of America

Luis Briones