Intel Corporation

Luis Briceno Guerrero

Bruce Querbach

Ali Muhtaroglu

Amjad M Khan

Mike J Tripp

Marco A Vindas Vargas

Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

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San José, Costa Rica

Luis Briceno Guerrero