Analog Devices,inc.

Advanced Micro Devices Corporation

Intel Corporation

Luis Antonio Basto

Juan Guillermo Revilla

Sankaran M Menon

Thomas Tomazin

Tien Dinh

Mark T Fox

W David Dougherty

Dwight Elmer Galbi

The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.

Method and apparatus for testing embedded cores

Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.

A universally accessible fully programmable memory built-in self-test (MBIST) system including an MBIST controller having an address generator configured to generate addresses for a memory under test, a sequencer circuit configured to deliver test data to selected addresses of the memory under test and reading out that test data, a comparator circuit configured to compare the test data read out of the memory under test to the test data delivered to the memory under test to identify a memory failure, and an externally accessible user programmable pattern register for providing a pattern of test data to the memory under test. The system includes an external pattern programming device configured to supply the pattern of test data to the user programmable data pattern register.

Universally accessible fully programmable memory built-in self-test (MBIST) system and method

According to the present invention, a method for inserting scan hardware into Integrated Circuits (IC) such as microcontrollers is disclosed. Custom scripts used by electronic design automation (EDA) tools are configured to accommodate those microcontroller designs that operate with multiple clocks and legacy cores. Furthermore, according to the present invention, custom script are used to provide buffering circuits to drive the scan hardware.

Insertion of scan hardware

A dual-edge pulse-triggered flip-flop comprising a gated data latch and a gated scan latch coupled in series with the data latch. In normal operation, the data latch captures a data input D in response to clock pulses ckp generated on each edge of a system clock ck. During an input scan operation, a selected stimulation bit presented on a scan input SI is transferred first into the scan latch in response to a scan input clock ak, and then into the data latch in response to a scan output clock bk. This stimulation bit is simultaneously presented on a scan output SO. During an output scan operation, a data bit Q presented on the scan input SI is transferred first into the scan latch in response to the scan input clock ak, and then into the data latch in response to the scan output clock bk. This data bit is simultaneously presented on the scan output SO. A scan chain can be formed by coupling the scan input SI of a first flip-flop to the scan output SO of a second, upstream flip-flop, and the scan output SO of the first flip-flop to the scan input SI of a third, downstream flip-flop.

High performance, low power, scannable flip-flop

A graphical user interface (GUI) provides a design engineer the capability of automatically inserting scan logic and test logic into a design. The graphical user interface includes a scan insertion option for a design engineer to invoke a scan insertion tool to check the design for testability. The graphical user interface also permits the design engineer to invoke a test generation tool such as an automatic test pattern generator (ATPG) tool to check the design for fault coverage. The graphical user interface, which can serve as a front end for a design framework, enables a design engineer to efficiently increase testability while still in a design phase.

Growing community of inventors

Austin, TX, United States of America

Luis Antonio Basto