Advanced Micro Devices Corporation

Spansion Llc.

Other

Globalfoundries Inc.

Advanced Micro Devices, Inc. and Spansion LLC

Lu You

Richard J Huang

Dawn M Hopper

Minh Van Ngo

Fei Wang

Minh Quoc Tran

Scott Allan Bell

Robert A Huertas

Pei-Yuan Gao

Srikanteswara Dakshina-Murthy

Suzette Keefe Pangrle

Mark S Chang

Simon S Chan

Pin-Chin Connie Wang

Lynne A Okada

Douglas J Bonser

Philip A Fisher

Paul Raymond Besser

Marina V Plat

Hao Fang

Alexander H Nickel

Hieu T Pham

Chih Yuh Yang

Marilyn I Wright

Hirokazu Tokuno

Erik Wilson

John JianShi Wang

Darin A Chan

King Wai Kelwin Ko

Angela Tai Hui

Christopher F Lyons

Sergey D Lopatin

Matthew S Buynoski

Robin W Cheung

Cyrus E Tabery

Khanh Q Tran

Christy M-c Woo

Jeremias D Romero

Mark T Ramsbey

Zoran Krivokapic

Calvin T Gabriel

Jeffrey Allan Shields

Shekhar Pramanick

John A Iacoponi

Jean Y Yang

Kent Kuohua Chang

Connie Pin-Chin Wang

Jacques J Bertrand

Richard C Nguyen

Mohammad R Rakhshandehroo

Christof Streck

Ramkumar Subramanian

Takeshi Nogami

James K Kai

Steven C Avanzino

Tuan Duc Pham

Michael K Templeton

William S Brennan

Amit P Marathe

Ning Cheng

Yi He

Chih-Yuh Yang

Kai Yang

Hartmut Ruelke

Joerg Hohage

Mario M Pelella

Guarionex Morales

Inkuk Kang

John G Pellerin

Minh-Van Ngo

Joffre F Bernard

Maria Chow Chan

Ercan Adem

Allen Lewis Evans

Kay Hellig

Robert J Chiu

Jerry Cheng

Amir Hossein Jafarpour

Terri Jo Kitson

Sung Jin Kim

Alline F Myers

Lothar Mergili

Steve Avanzino

Kei-Leong Ho

Pin Chin Connie Wang

Brian Mooney

Jean Yei-Mei Yang

A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Mask for forming integrated circuit

During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 &#x212b; to about 500 &#x212b;, curing after deposition, as by UV radiation or by heating at a temperature of about 400&#xb0; C. to about 1000&#xb0; C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

Gap-filling with uniform properties

A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% Nwith less than 10% H, performing planarization, performing in-situ low-H NHplasma treatment and low Si&#x2014;H SiN etch stop layer deposition, and performing remaining back end processing.

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Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an Natmosphere containing low Hor no H, and at temperatures less than 200&#xb0; C., e.g., 100&#xb0; C. to 150&#xb0; C.

Cu annealing for improved data retention in flash memory devices

Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si&#x2014;H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si&#x2014;H bonds on the first silicon nitride layer for reduced charge loss.

Semiconductor devices with copper interconnects and composite silicon nitride capping layers

Method for forming integrated circuit

According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.

Disposable spacer process for field effect transistor fabrication

A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Method for manufacturing a memory device having a nanocrystal charge storage region

A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.

Memory device having a nanocrystal charge storage region and method

An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.

Ultra low dielectric constant integrated circuit system

Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.

Sealing sidewall pores in low-k dielectrics

A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes

An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition

The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices

Growing community of inventors

San Jose, CA, United States of America

Lu You