Ampsource Biopharma Shanghai Inc.

Integrated Device Technology, Inc.

Lu Yang

Qiang Li

Yuncheng Zheng

Xinlu Ma

Yuanli Li

Si Ruo Chen

Yongjuan Gao

Zhu Wang

Naichao Sun

Zhao Dong

Zirui Li

Xiaoqian Zhang

Sibing Wang

A linker peptide for constructing a fusion protein. The linker peptide comprises a flexible peptide and a rigid peptide. The flexible peptide consists of one or more flexible units. The rigid peptide consists of one or more rigid units. The flexible unit comprises two or more amino acid residues selected from Gly, Ser, Ala, and Thr. The rigid unit comprises a human chorionic gonadotropin &#x3b2;-subunit carboxy-terminal peptide (CTP) bearing a plurality of glycosylation sites. The linker peptide can more effectively eliminate mutual steric hindrance of two fusion molecules, decreasing a reduction/loss of polymerization or activity resulting from improper folding of an active protein or a conformational change. On the other hand, the negatively charged, highly sialylated CTP can resist renal clearance, further prolonging a half-life of a fused molecule and enhancing bioavailability of a fused protein. Furthermore, a protective effect of a glycosylated side chain CTP can lower the protease sensitivity of the linker peptide, making a linker region of the fusion protein less degradable.

Linker peptide for constructing fusion protein

This disclosure provides an antibody specifically binding to PD-1 with high affinity. Also provided are a nucleic acid molecule for coding the antibody, an expression vector and a host cell for expressing the antibody, and a production method for the antibody. In addition, also provided are an immunoconjugate and a pharmaceutical composition comprising the antibody and use of the antibody in preparation of drugs for treating cancers, infectious diseases, and inflammatory diseases.

Anti-PD-1 antibody and use thereof

A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

Method and circuit for DisplayPort video clock recovery

Growing community of inventors

Shanghai, China

Lu Yang