Memc Electronic Materials, Inc.

Globalwafers Co., Ltd.

Sunedison Semiconductor Limited

Sunedison Semiconductor Limited (uen201334164h)

Lu Fei

Jeffrey Louis Libbert

Robert J Falster

Shawn George Thomas

Gang Wang

Igor Peidous

Harold W Korb

Joseph C Holzer

Srikanth Kommu

Andrew Marquis Jones

Alex Usenko

John Allen Pitney

Luciano Mule'Stagno

Ichiro Yoshimura

Robert Wendell Standley

Luciano Mule&prime;Stagno

Andrew M Jones

A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

High resistivity semiconductor-on-insulator wafer and a method of manufacture

High resistivity semiconductor-on-insulator wafer and a method of manufacturing

This invention generally relates to a process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.

Method to delineate crystal related defects

Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.

Methods for producing silicon on insulator structures having high resistivity regions in the handle wafer

Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Methods for monitoring the amount of metal contamination in a process

The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.

Methods for reducing the width of the unbonded region in SOI structures

Semiconductor wafers with reduced roll-off and bonded and unbonded SOI structures produced from same

Methods for monitoring the amount of contamination imparted into semiconductor wafers during wafer processing

Epitaxial wafers comprising a single crystal silicon substrate comprising agglomerated vacancy defects and having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated intrinsic point defects on the substrate surface upon which the epitaxial layer is deposited.

Single crystal silicon wafer having an epitaxial layer substantially free from grown-in defects

The present invention is directed to an epitaxial wafer comprising a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.

Epitaxial wafer substantially free of grown-in defects

The present invention is directed to a set of epitaxial silicon wafers assembled in a wafer cassette, boat or other wafer carrier. Each wafer comprises a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.

Epitaxial silicon wafers substantially free of grown-in defects

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St. Louis, MO, United States of America

Lu Fei