United Microelectronics Corp.

Novatek Microelectronics Corps.

Lu-An Chen

Tien-Hao Tang

Tai-Hsiang Lai

Li-Cih Wang

Yi-Chun Chen

Mei-Ling Chao

Ya-Ting Lin

Yi-Ning He

Kuan-Cheng Su

Chang-Tzu Wang

Jhih-Ming Wang

Tung-Hao Sung

Kun-Jheng Wu

The present invention provides an ESD protection circuit electrically connected between a high voltage power line and a low voltage power line, and the ESD protection circuit includes a bipolar junction transistor (BJT) and a trigger source. A collector of the BJT is electrically connected to the high voltage power line, and an emitter and a base of the BJT are electrically connected to the low voltage power line. The trigger source is electrically connected between the base of the BJT and the high voltage power line.

Electrostatic discharge protection circuit

A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate in the substrate, at least a first doped region formed in the drain region, and at least a first well having the first doped region formed therein. The source region and the drain region include a first conductivity type, the first doped region and the first well include a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other.

Semiconductor device for electrostatic discharge protection

An electrostatic discharge (ESD) protection control circuit for an output pad of an integrated circuit includes an output driver and a control switch. The output driver, coupled to the output pad, includes a first output transistor for outputting power or signals to the output pad. The control switch, for improving ESD protection on the output pad when closed, includes a first connection terminal, coupled to a gate terminal of the first output transistor; a second connection terminal, coupled to a ground terminal; and a control terminal, coupled to a first power supply terminal.

ESD protection control circuit and system

A laterally diffused metal oxide semiconductor (LDMOS) is provided. A substrate has a deep well with a second conductive type therein. A gate is disposed on the substrate. A first doped region of a second conductive type and a second doped region of a first conductive type are located in the deep well and at the corresponding two sides of the gate. A drain region of a second conductive type is located in the first doped region. A drain contact is disposed on the drain region. A doped region of a first conductive type is located in the first doped region and under the drain region but not directly below the drain contact. A source region is located in the second doped region. A field drift metal oxide semiconductor (FDMOS) which is similar to the laterally diffused metal oxide semiconductor (LDMOS) is also provided.

Laterally diffused metal oxide semiconductor and field drift metal oxide semiconductor

The present invention provides electrostatic discharge protectors. One aspect of the present invention provides an electrostatic discharge protector includes a substrate, an electrostatic discharge protection circuit disposed on the substrate, and a pickup ring surrounding the electrostatic discharge protection circuit. The pickup ring has a plurality of low resistance zones where a doping layer, a contact and a metal layer are connected in sequence, and the low resistance zones are distributed within the pickup ring separately and unequally.

Electrostatic discharge protector

An electrostatic discharge protection structure comprises an isolation layer, a high voltage P-well, an N-well, a P-well, a first doped region of N-type conductivity, a second doped region of P-type conductivity, a third doped region of N-type conductivity, a fourth doped region of P-type conductivity, an anode, and a cathode. The isolation layer is disposed on a substrate. The high voltage P-well is disposed on the isolation layer. The N-well is disposed in the high voltage P-well. The P-well is disposed in the high voltage P-well, and the P-well is separated from the N-well. The first and the second doped regions are disposed in the N-well. The third and the fourth doped regions are disposed in the P-well. The anode is electrically connected to the first doped region and the second doped region, and the cathode is electrically connected to the fourth doped region.

Electrostatic discharge protection structure capable of preventing latch-up issue caused by unexpected noise

A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively sides of the gate, a first well region formed in the substrate, and a plurality of first doped islands formed in the source region. The drain region and the source region include a first conductivity, and the first well region and the first doped islands include a second conductivity. The source region is formed in the first well region, and the first doped islands are spaced apart from the first well region.

Semiconductor device

The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region.

Transistor structure for electrostatic discharge protection

A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

An electrostatic discharge (ESD) protection device is disclosed. The ESD protection device comprises a trigger circuit, a switch, and an output buffer. When an ESD event occurs, the trigger circuit turns on the switch. One part of the current of the electrostatic discharge (ESD) event may be routed to a ground through the switch from the output buffer coupled to the output pad.

Electrostatic discharge (ESD) protection device for an output buffer

An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region.

A stacked electrostatic discharge (ESD) protection device includes a substrate; a deep well with a first conductive type formed in the substrate, the deep well defining a plurality of element regions with a second conductive type therein; and a plurality of ESD protection elements, each of which is formed in one of the element regions. A current path is formed by connecting the plurality of ESD protection elements in series.

Stacked electrostatic discharge (ESD) protection device

A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Electrostatic discharge protection semiconductor device

The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.

Growing community of inventors

Hsinchu County, Taiwan

Lu-An Chen