Adeia Semiconductor Bonding Technologies Inc.

Loreto Cantillep

Scott P McGrath

Terrence Caskey

Marc E Robinson

Simon J S McElrea

Scott Jay Crane

Lawrence Douglas Andrews, Jr

Suzette Keefe Pangrle

Jeffrey S Leal

Simon McElrea

Ravi Shenoy

Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

Stacked die assembly having reduced stress electrical interconnects

In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.

Electrically interconnected stacked die assemblies

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San Jose, CA, United States of America

Loreto Cantillep