Government of the United States of America, as Represented by the Secretary of Commerce

Other

Loren W Linholm

Richard A Allen

Michael W Cresswell

William B Penzes

E Clayton Teague

Jeffry Joseph Sniegowski

Michael Gaitan

R N Ghoshtagore

Martin C Peckerar

Joseph J Kopanski

Colleen H Ellenwood

Imaging instruments for inspecting products, such as semiconductor chips, are calibrated by providing a reference test structure having features which can be located by optical measurements not subject to tool-induced shift and wafer-induced shift experienced by the imaging instrument, thereby enbabling self correction of the imaging instrument. The reference test structure, which has a plurality of target units formed therein, is first qualified using the optical measurements, and is then used to calibrate the imaging instrument. The optical measurements may be made by a supplementary alternative imaging-sensor means which can be integrated into existing imaging instrument architecture. A series of test structure elements may be fabricated with one component of each being spaced at progressively greater distances from an arbitrary baseline, such that a zero overlay element may be identified by the alternative imaging sensor means.

Overlay target and measurement procedure to enable self-correction for

An improved test structure for measurement of width of conductive lines formed on substrates as performed in semiconductor fabrication, and an improved reference grid for calibrating instruments for such measurements, is formed from a monocrystalline starting material, having an insulative layer formed beneath its surface by ion implantation or the equivalent, leaving a monocrystalline layer on the surface. The monocrystalline surface layer is then processed by preferential etching to accurately define components of the test structure. The substrate can be removed from the rear side of the insulative layer to form a transparent window, such that the test structure can be inspected by transmissive-optical techniques. Measurements made using electrical and optical techniques can be correlated with other measurements, including measurements made using scanning probe microscopy. Nested quadrilateral calibration reference grids particularly useful in calibrating optical coordinate measurement instruments are disclosed.

Monocrystalline test and reference structures, and use for calibrating

A test structure for submicrometer metrology as used in integrated circuit manufacture comprises a bridge conductor divided into three segments by pairs of voltage taps. A first segment has no intermediate taps; a second segment has a number of dummy taps intermediate its ends; and a third segment has a single central tap, which may typically be formed in a different step than the remainder of the test structure, intermediate its ends. Preferably, the central tap extends from the same side of the bridge conductor as the taps at the ends of the third segment thereof. In order to evaluate a manufacturing operation, for example, to monitor the accuracy of registration of successive manufacturing steps, test signals are applied successively between the pairs of pads. Comparison of the response of the first and second segments to the test signals allows evaluation of the segment-shortening effect of the taps; comparison of the response of the two portions of the third segment to the test signals allows evaluation of their lengths, and thus of the offset, that is, the accuracy of registration of the step used to form the central tap. A plurality of substantially identical test structures are formed, for example, on an integrated circuit substrate. Offsets measured with respect to each of the substrates are summed using a least-squares technique, to allow separation of tool-wide misalignment errors and errors in the generation of a particular pattern or similar tool used to form a test structure. By summing the offsets measured with respect to a large number of test structures, random errors due to the presence of dust or other contaminants on the tools are effectively eliminated. The test structure according to the invention may also be used to calibrate optical measurements, or may be implemented as a line scale for direct optical measurements.

Electrical test structure and method for measuring the relative

An improved test structure for measurement of width of conductive lines formed on substrates as performed in semiconductor fabrication, and for calibrating instruments for such measurements, is formed from a monocrystalline starting material, having an insulative layer formed beneath its surface by ion implantation or the equivalent, leaving a monocrystalline layer on the surface. The monocrystalline surface layer is then processed by preferential etching to accurately define components of the test structure. The substrate can be removed from the rear side of the insulative layer to form a transparent window, such that the test structure can be inspected by transmissive-optical techniques. Measurements made using electrical and optical techniques can be correlated with other measurements, including measurements made using scanning probe microscopy.

Monocrystalline test structures, and use for calibrating instruments

Imaging instruments for inspecting products, such as semiconductor chips, are calibrated by providing a reference test structure having features which can be located by electrical measurements not subject to tool-induced shift and wafer-induced shift experienced by the imaging instrument. The reference test structure is first qualified using electrical measurements, and is then used to calibrate the imaging instrument. The electrical measurements may be made by forcing a current between a plurality of spaced reference features and an underlying conductor, or may be made by capacitive, conductive, magnetic, or impedance-measuring techniques. Capacitive techniques may also be used to detect features not susceptible of resistance measurement, such as dielectric or insulative materials, or metallic structures not accessible for forcing a current therethrough. A series of test structure elements may be fabricated with one component of each being spaced at progressively greater distances from an arbitrary baseline, such that a null-overlay element may be identified.

Method and reference standards for measuring overlay in multilayer

A test structure for submicrometer metrology as used in integral circuit manufacture comprises a bridge conductor divided into three segments by pairs of voltage taps. A first segment has no intermediate taps; a second segment has a number of dummy taps intermediate its ends; and a third segment has a single central tap, which may typically be formed in a different step than the remainder of the test structure, intermediate its ends. Preferably, the central tap extends from the same side of the bridge conductor as the taps at the ends of the third segment thereof. In order to evaluate a manufacturing operation, for example, to monitor the accuracy of registration of successive manufacturing steps, test signals are applied successively between the pairs of pads. Comparison of the response of the first and second segments to the test signals allows evaluation of the segment-shortening effect of the taps; comparison of the response of the two portions of the third segment to the test signals allows evaluation of their lengths, and thus of the offset, that is, the accuracy of registration of the step used to form the central tap. A plurality of substantially identical test structures are formed, for example, on an integrated circuit substrate. Offsets measured with respect to each of the substrates are summed using a least-squares technique, to allow separation of tool-wide misalignment errors and errors in the generation of a particular pattern or similar tool used to form a test structure. By summing the offsets measured with respect to a large number of test structures, random errors due to the presence of dust or other contaminants on the tools are effectively eliminated.

A test structure for submicrometer metrology as used in integrated circuit manufacture comprises a bridge conductor divided into three segments by pairs of voltage taps. A first segment has no intermediate taps; a second segment has a number of dummy taps intermediate its ends; and a third segment has a single central tap, which may typically be formed in a different step than the remainder of the test structure, intermediate its ends. Preferably, the central tap extends from the same side of the bridge conductor as the taps at the ends of the third segment thereof. In order to evaluate a manufacturing operation, for example, to monitor the accuracy of registration of successive manufacturing steps, test signals are applied successively between the pairs of pads. Comparison of the response of the first and second segments to the test signals allows evaluation of the segment shortening effect of the taps; comparison of the response of the two portions of the third segment to the test signals allows evaluation of their lengths, and thus of the accuracy of registration of the step used to form the central tap.

A prepatterned potentiometer precursor includes a precursor substrate; and at least two spaced apart potentiometer precursor patterns on the substrate, each potentiometer precursor pattern including a bridge, two substantially similar end taps transverse to and extending from the bridge, and a center tap transverse to and extending from the bridge and centrally disposed between the end taps wherein the center taps of the bridges are substantially parallel to each other and are substantially wider than the end taps. A method of determining the distance between test features of test patterns on a test piece includes preparing a precursor substrate including at least two electrically conducting spaced apart potentiometer precursor patterns, each potentiometer precursor pattern including a bridge, two substantially similar end taps transverse to and extending from the bridge, and a center tap transverse to and extending from the bridge and centrally disposed between the end taps.

Method of and articles for accurately determining relative positions of

A test structure pattern and method for processing the electrical data extracted from the pattern which allows for the measurement of a short line with a precision on the order of 10 nanometers.

Linewidth micro-bridge test structure

A system which samples and records the locations of opaque particles accumulating on a surface. The system represents graphically the geometrical distributions of the particles through an integral electronic hardware/software subsystem. The key component is a radiant energy sensitive sensor which produces the sampling surface. The sensor is exposed to a constant level of radiant energy. Opaque particles becoming resident upon the sensor surface inhibit sensitization of the surface by the radiant energy and thereby indicates the presence and location of the particle. Embodiments of the sensor include charge coupled devices (CCDs), photodiode arrays, intrinsic or extrinsic 'bulk' material, and optically- or UV-erasable memories.

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Ijamsville, MD, United States of America

Loren W Linholm