International Business Machines Corporation

Infineon Technologies Ag

Globalfoundries U.S. Inc.

Lloyd G Burrell

Wolfgang Sauter

Kwong Hon Wong

Anthony K Stamper

Jeffrey P Gambino

Louis L Hsu

Baozhen Li

Hans-Joachim Barth

Hyun K Lee

Stephen Ellinwood Luce

Thomas L McDevitt

Howard Hao Chen

John E Heidenreich, Iii

Mark D Levy

Sally J Yankee

Edward E Cooney, Iii

Sanjay C Mehta

Toyohiro Aoki

Sarah Huffsmith Knickerbocker

William Francis Landers

Charles Robert Davis

Henry Atkinson Nye, Iii

Douglas Wayne Kemerer

Ronald Dean Goldblatt

Gerald R Friese

Joseph L Chan

Samuel McKnight

Jorge A Lubguban

Emmanuel F Crabbe

Adreanne Kelly

David K Anderson

Michael Stetter

Matthew C Gorfien

John J Garant

Wolfgang c/oIBM Uk Limited Int propLaw Sauter

A bonding structure for a semiconductor substrate and related method are provided. The bonding structure includes a first oxide layer on the semiconductor substrate, and a second oxide layer on the first oxide layer, the second oxide layer for bonding to another structure. The second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer. The second oxide layer may also have a higher density than the first oxide layer. The bonding structure can be used to bond chips to wafer or wafer to wafer and provides a greater bond strength than just a thick oxide layer.

Bonding structure using two oxide layers with different stress levels, and related method

Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

Methods for forming co-planar wafer-scale chip packages

A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

Method of fabricating a wire bond pad with Ni/Au metallization

A sensor for measuring cracks in a semiconductor device, such as a wafer and, more particularly, to a BEOL wirebond crack sensor for low-k dies or wafers, and a method of providing the wirebond crack sensor for low-k wafers or the like structures.

Wirebond crack sensor for low-k die

Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

Copper to aluminum interlayer interconnect using stud and via liner

A semiconductor device, and a method of fabricating the device, having a copper wiring level and an aluminum bond pad above the copper wiring level. In addition to a barrier layer which is normally present to protect the copper wiring level, there is a composite layer between the aluminum bond pad and the barrier layer to make the aluminum bond pad more robust so as to withstand the forces of bonding and probing. The composite layer is a sandwich of a refractory metal and a refractory metal nitride.

Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad

A semiconductor device () having support structures () beneath wirebond regions () of contact pads () and a method of forming same. Low modulus dielectric layers () are disposed over a workpiece (). Support structures () are formed in the low modulus dielectric layers (), and support vias () are formed between the support structures (). A high modulus dielectric film () is disposed between each low modulus dielectric layer (), and a high modulus dielectric layer () is disposed over the top low modulus dielectric layer (). Contact pads () are formed in the high modulus dielectric layer (). Each support via () within the low modulus dielectric layer () resides directly above a support via () in the underlying low modulus dielectric layer (), to form a plurality of via support stacks within the low modulus dielectric layers ().

Support structures for wirebond regions of contact pads over low modulus materials

A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

Process for forming fusible links

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Poughkeepsie, NY, United States of America

Lloyd G Burrell