Qualcomm Incorporated

Liyong Wang

Kuljit Singh Bains

Wesley Queen

Raj K Ramanujan

Lew G Chua-Eoan

Jian Shen

Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.

Apparatus and method for performing persistent write operations using a persistent write command

A processing system for performing persistent write operations comprises a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host. Persistent Write completion indications may be provided to the host in a different order from an order in which corresponding commands were received. Statuses of Persistent Write commands may be maintained in a completed bitmap or a pending bitmap. A FLUSH command may be provided to indicate that all prior writes buffered in volatile media are to be pushed to non-volatile or persistent memory. The memory system may include a non-volatile dual in-line memory module which supports Persistent Writes (NVDIMM).

In non-energy-backed memory with persistent storage, a complex protocol is required to handle persistent writes. To address this issue, it is proposed to provide a simple protocol to handle persistent writes in energy-backed memory with persistent storage.

Persistent write data for energy-backed memory

Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.

Write credits management for non-volatile memory

Aspects of the disclosure are directed to providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory. Accordingly, the apparatus and method may include determining data rate mode selection criteria; selecting a data rate mode based on the data rate mode selection criteria; configuring a host interface for the data rate mode; and configuring an RCD input interface for the data rate mode. In one aspect, the apparatus and method further include activating a clock signal on the host interface and on the RCD input interface; transferring data from the host interface to the RCD input interface using the clock signal; and transferring the data from an RCD output interface using the clock signal in either 1N mode or 2N mode. And, the data rate mode is one of the SDR mode or the DDR mode.

Providing single data rate (SDR) mode or double data rate (DDR) mode for the command and address (CA) bus of registering clock drive (RCD) for dynamic random access memory (DRAM)

Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems is disclosed. In one aspect, a processor-based system includes a DRAM circuit (e.g., disposed on a common x4/x8 die) providing 4-bit-wide data access ('x4') and a 128-bit internal data prefetch. When operated in a x4 mode, the DRAM circuit is configured to provide an extended DRAM burst length of 32 bits ('BL32'). The DRAM circuit receives a memory read request from a memory controller communicatively coupled to the DRAM circuit, prefetches 128 bits of data, and returns all of the 128 bits of fetched data to the memory controller in response to the memory read request. In some aspects, the DRAM circuit may also receive a memory write command including 128 bits of write data from the memory controller, and write the 128 bits of write data to memory without performing a read/modify/write (RMW) operation.

Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems

According to various aspects, a memory controller may schedule ZQ commands to periodically calibrate individual memory ranks in a multi-rank memory. The memory controller may schedule a ZQ short command at each ZQ interval and record that the ZQ short command was missed with respect to a memory rank in a self-refresh mode at the ZQ interval. After the missed ZQ short commands reaches a first threshold, a ZQ long command may be scheduled at the next ZQ interval and normal ZQ behavior may resume in the event that the memory rank exits the self-refresh mode and the ZQ long command is executed. However, if the memory rank stays in the self-refresh mode until missed ZQ long commands reaches a second threshold, the memory controller may trigger a ZQ long command once the memory rank exits the self-refresh mode and skip a next ZQ calibration before resuming normal ZQ behavior.

Periodic ZQ calibration with traffic-based self-refresh in a multi-rank DDR system

A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.

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Cary, NC, United States of America

Liyong Wang