International Business Machines Corporation

Liudi Wang

Li Liu

Hailong Li

Yin Lu

Jixiang Hou

A method for constructing a scan chain for a memory sequential test, including determining an input boundary register of the memory; determining a number N of test vectors required according to the type of the memory input pins to which the input boundary register is connected; arranging the scan chain based on the number N, such that in the scan chain, upstream of the input boundary register and immediately adjacent to the input boundary register, there are at least (N&#x2212;1) continuous non-boundary registers; and setting control signals of the input boundary register and the (N&#x2212;1) non-boundary registers to make them receive scan test input as test vectors under memory sequential test mode.

Growing community of inventors

Beijing, China

Liudi Wang