Cadence Design Systems, Inc.

Liqun Deng

Pinhong Chen

Miao Liu

Richard M Chou

Fangfang Li

Yufeng Luo

Jieqian Yu

Hanqi Yang

Ximing Zhou

Chin-Chih Chang

Guozhi Xu

Disclosed is an improved approach for efficiently implementing a three-dimensional integrated circuit (3D-IC) design with heterogeneous and/or homogeneous dies. A first die design and a second die design in a three-dimensional (3D) electronic design maybe identified, and a wrapper design may be generated for at least a block of circuit component designs in the second die design for concurrent implementation of both the first and the second die designs. Both the first and the second dies of the 3D electronic design are concurrently implemented based at least upon a floorplan that is generated with at least the wrapper design for the 3D electronic design. A first wrapper and a second wrapper may be respectively generated for the first die design and the second die design based at least in part upon a result of the concurrent implementation.

Methods, systems, and computer program products for efficiently implementing a 3D-IC

Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.

Electronic design 3D mixed placement and unfolding

Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.

Concurrent optimization of 3D-IC with asymmetrical routing layers

Growing community of inventors

Shanghai, China

Liqun Deng