Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Lionel D'Luna

Sathish Kumar Radhakrishnan

Thomas A Hughes

Mark Chambers

Kwang Young Kim

Sathish Kumar

Lakshmanan Ramakrishnan

Francis Cheung

Kenneth R Kindsfater

Anand Pande

Tom Hughes

A single chip set-top box system and method is provided. The system comprises, for example, a transceiver, an audio/video decoder, a CPU, peripherals, DAVIC MAC and a graphics processor. The transceiver receives a digitally modulated compressed audio/video signal, and the audio/video decoder receives the compressed audio/video signal from the transceiver and decompresses the compressed audio/video signal. The graphics processor blends the decompressed audio/video signal with graphics to generate a blended video image with audio.

Single chip set-top box system

A system and method are used to allow high speed communication between a circuit and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Phase controlled high speed interfaces

A method and system for testing a memory controller are provided herein. A test sequence may be generated within the memory controller. A test output may also be generated within the memory controller, where the test output is associated with the test sequence. The test output may then be verified. The test sequence may comprise one or more of a control command, a memory address, and/or a DQM signal. The test output may be generated by a sequencer. The test output may be verified by a cyclic redundancy check (CRC) module. The test sequence may also comprise random write data. The random write data may be communicated to a memory controller write data output via a write data bus.

Custom logic BIST for memory controller

A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal. These subsequent delay device clock signals are transmitted to the aligning device and to the sequencer before each transfer occurs.

System and method to align clock signals

A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and placing the synthesized/laid out portion and the replicated portions in proximity to a corresponding plurality of pads.

Byte slice based DDR timing closure

Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.

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Irvine, CA, United States of America

Lionel D'Luna