Power Integrations, Inc.

Emcore Corporation

Velox Semiconductor Corporation

LinLin Liu

Jamal Ramdani

Alexey Kudymov

Milan Pophristic

John Paul Edwards

Alex D Ceruzzi

Michael Murphy

Bryan S Shelton

Xiaohui Wang

Richard A Stall

Xiang Gao

Boris Peres

Mark Gottfried

Stephen Schwed

Douglas Collins

Marek Pabisz

Elaine Taylor

TingGang Zhu

Ivan Eliashevich

Ting Gang Zhu

Steve Schwed

A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Asymmetrical plug technique for GaN devices

An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Method of fabricating a transistor

Protective insulator for HFET devices

A high-voltage field effect transistor (HFET) includes a first active layer, a second active layer, and a layer of electrical charge disposed proximate to the first active layer and the second active layer. A gate dielectric is disposed proximate to the second active layer. A contact region in the HFET includes a contact coupled to supply or withdraw charge from the HFET, and a passivation layer disposed proximate to the contact and the gate dielectric. An interconnect extends through the passivation layer and is coupled to the contact. An interlayer dielectric is disposed proximate to the interconnect, and a plug extends into the interlayer dielectric and is coupled to the first portion of the interconnect.

Contact plug for high-voltage devices

A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. The first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer. A gate dielectric disposed between the second semiconductor material and the first passivation layer. A gate electrode is disposed above the gate dielectric. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material.

A high-voltage field effect transistor (HFET) includes a first semiconductor material, a second semiconductor material, and a heterojunction. The heterojunction is disposed between the first semiconductor material and the second semiconductor material. The HFET also includes a plurality of composite passivation layers, where a first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. A gate dielectric is disposed between the first passivation layer and the second semiconductor material. A gate electrode is disposed between the gate dielectric and the first passivation layer. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a source field plate is coupled to the source electrode.

High-electron-mobility transistors that include field plates are described. In a first implementation, a HEMT includes a first and a second semiconductor material disposed to form a heterojunction at which a two-dimensional electron gas arises and source, a drain, and gate electrodes. The gate electrode is disposed to regulate conduction in the heterojunction between the source electrode and the drain electrode. The gate has a drain-side edge. A gate-connected field plate is disposed above a drain-side edge of the gate electrode and extends laterally toward the drain. A second field plate is disposed above a drain-side edge of the gate-connected field plate and extends laterally toward the drain.

High-electron-mobility transistors

A GaN HFET includes a silicon substrate with an AlOlayer above the silicon substrate. The AlOlayer has voids formed therein. A plurality of alternating GaN and AlN layers are above the AlOlayer. The GaN and AlN layers are under continuous compressive stress.

High-quality GaN high-voltage HFETs on silicon

A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.

Method of fabricating GaN high voltage HFET with passivation plus gate dielectric multilayer structure

Substrates of GaN over silicon suitable for forming electronics devices such as heterostructure field effect transistors (HFETs), and methods of making the substrates, are disclosed. Voids in a crystalline AlOfilm on a top surface of a silicon wafer are formed. The top surface of the silicon wafer is along the &#x3c;111&#x3e; silicon crystal orientation. A plurality of laminate layers is deposited over the voids and the AlOfilm. Each laminate layer includes an AlN film and a GaN film. A transistor or other device may be formed in the top GaN film.

High quality GaN high-voltage HFETs on silicon

A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.

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Hillsborough, NJ, United States of America

LinLin Liu