Shanghai Huali Integrated Circuit Mfg. Co., Ltd.

Shanghai Huali Integrated Circuit Corporation

Lingye Yang

Li Sun

Jinde Gao

Hai'an Liu

The present application provides a failure analysis and location method for a short circuit structure. a first layer metal wire structure and a second layer metal wire structure located above the first layer metal wire structure, the first and second layer metal wire structures are connected by a first layer metal via located between the first and second layer metal wire structures; a second layer metal via located above the second layer metal wire structure and connected to the second layer metal wire structure. A VC anomaly in the semiconductor structure is roughly located to find a failure region. The failure region is plated with a conductive material layer to connect the second layer metal via to the conductive material layer, wherein when an abnormal VC is found at a position on the cross-section of the sample, a failure point at the position is accurately located.

Failure analysis and location method for short circuit structure

The present invention provides a method for positioning short circuit failure, used to position the short circuit point between a first metal wire and a second metal wire. The positioning method comprises: measuring the resistance between the first metal wire and the second metal wire, and positioning the first region where the short circuit point is located by a resistance ratio. In the first region, the short circuit point may be gradually approached by periodically cutting the first metal wire and the second metal wire, electrically isolating the cut portions, and performing a plurality of voltage contrast analysis on the first metal wire and the second metal wire based on the principle of the dichotomy, thereby accurately locating the short circuit point. With the positioning method provided by the present invention, the region where the short circuit defect of the nA (nano ampere) level is located may be accurately found from the first metal wire and the second metal wire that are extremely long. The present invention contributes to improving the yield of a semiconductor device based on the defect adjustment process.

Method for positioning short circuit failure

A failure positioning method for positioning leakage defect cell between the gate and the active region of transistor cells arranged in an array. The positioning method includes the steps of: measuring the resistance between a first metal wire connecting the active regions and a second metal wire connecting the gates, and positioning a first region where the defect cell is located by resistance ratio; electrically isolating the active region contact holes and the gate contact holes from each other; shorting the gate contact holes in the first region; and performing active voltage contrast analysis on the plurality of columns of transistor cells in the first region to position the leakage defect in the first region by comparing the voltage contrast images. With the positioning method, the transistor cell having a leakage defect at nA level may be accurately found from a plurality of transistor cells arranged in an array. The positioning method helps to improve the yield of semiconductor device based on the above defect adjustment process.

Growing community of inventors

Shanghai, China

Lingye Yang