Texas Instruments Corporation

International Business Machines Corporation

Stmicroelectronics Gmbh

Other

Globalfoundries Inc.

Air Liquide America, L.p.

Lindsey H Hall

Scott Robert Summerfelt

Haowen Bu

Jennifer A Sees

Jiong-Ping Lu

Kezhakkedath Ramunni Udayakumar

Sanjeev Aggarwal

Francis Gabriel Celii

Shaofeng Yu

Theodore Sidney Moise

Ashutosh Misra

Pr Chidambaram

Ahmet Serkan Ozcan

Kelly Jay Taylor

Trace Quentin Hurd

Filippos Papadatos

Donald S Miles

Clint Montgomery

Michael Hatzistergos

Jagdish Prasad

Yiyi Wang

Luigi Colombo

Mark R Visokay

Douglas Ticknor Grider

Freidoon Mehrad

Rajesh B Khamankar

Shashank Sureshchandra Ekbote

Yaw S Obeng

Scott David Johnson

Satyavolu Srinivas Papa Rao

Robert Kraft

Steven R Soss

Randolph F Knarr

Deborah J Riley

Brett H Engel

Ajith Varghese

Lance Stanford Robertson

Duofeng Yue

Borna J Obradovic

Jin Zheng Wallner

K R Udayakumar

David F Hilscher

Craig Henry Huffman

Brian Ashley Smith

Juanita DeLoach

J Scott Martin

Vivian Liu

Thomas D Bonifiield

Sirisha Kuchimanchi

Charles R Schraeder

Oliver Chyan

A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

Method to improve semiconductor surfaces and polishing

A method of forming overlapping contacts in a semiconductor device includes forming a first contact in a dielectric layer; etching the dielectric layer to form a recess adjacent to the first contact and removing a top portion of the first contact while etching the dielectric layer, wherein a bottom portion of the first contact remains in the dielectric layer after the recess is formed in the dielectric layer; and forming a second contact in the recess adjacent to the bottom portion of the first contact and on top of a top surface of the bottom portion of the first contact.

Overlapping contacts for semiconductor device

Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

Mitigation of gate to contact capacitance in CMOS flow

A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.

Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean

A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Method for cleaning post-etch noble metal residues

A method of forming an integrated circuit transistor (). The method provides a first semiconductor region () and forms () a gate structure () in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (). The method also forms at least a first layer () adjacent the first sidewall and the second sidewall. The method also forms () at least one recess () in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing () the at least one recess such that an oxidized material is formed therein, second, stripping () at least a portion of the oxidized material, and third, forming () a second semiconductor region () in the at least one recess.

Recessed drain extensions in transistor device

The present invention substantially removes dry etch residue from a dry plasma etch processprior to depositing a cobalt layeron silicon substrate and/or polysilicon material. Subsequently, one or more annealing processesare performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operationand then an extended cleaning operationthat includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operationis performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation

Process method to facilitate silicidation

The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes forming fluorine containing regions () in the source/drain regions () employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer () over the substrate () and fluorine containing regions (), and reacting the metal layer () with the fluorine containing regions () to form metal silicide regions () in the source/drain regions ().

Method for manufacturing a semiconductor device containing metal silicide regions

The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device () , among other steps, includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes subjecting the gate structure () and substrate () to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains () subsequent to subjecting the gate structure () and substrate () to the dry etch process. Thereafter, the method includes forming metal silicide regions () in the gate structure () and the fluorinated source/drains ().

Method for manufacturing a semiconductor device having silicided regions

The present invention provides a process of manufacturing a semiconductor devicewhile reducing silicon loss. In one aspect, the process includes removing a photoresist layerfrom a semiconductor substrateadjacent a gateand cleaning the semiconductor substrate with a wet clean solution. The removing step includes subjecting the photoresist layerto a plasma ash. The plasma ash removes at least a portion of a crustformed on the photoresist layerbut leaves a substantial portion of the photoresist layer. The photoresist layeris subjected to a wet etch subsequent to the plasma ash that removes a substantial portion of the photoresist layer

Silicon recess improvement through improved post implant resist removal and cleans

The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode () over a substrate (), the capped polysilicon gate electrode () including a buffer layer () located between a polysilicon gate electrode layer () and a protective layer (). The method further includes forming source/drain regions () in the substrate () proximate the capped polysilicon gate electrode (), removing the protective layer () and the buffer layer (), and siliciding the polysilicon gate electrode layer () to form a silicided gate electrode ().

Method for manufacturing a silicided gate electrode using a buffer layer

One aspect of the invention relates to a method of cleaning high density capacitors. According to the method, the capacitors are cleaned with a plasma that includes fluorine-containing radicals. The plasma removes a small layer from the capacitors, including their sidewalls, and thereby removes surface contaminants. The method is effective even when the capacitors include hard-to-etch dielectric materials, such as tantalum and hafnium oxides. In a preferred embodiment, the plasma clean is combined with a solvent clean.

Clean for high density capacitors

Growing community of inventors

Plano, TX, United States of America

Lindsey H Hall