Avogy, Inc.

Xerox Corporation

Nanosys, Inc.

Glo Ab

Philips Lumileds Lighting Company LLC

Lumileds LLC

Koninklijke Philips Corporation N.v.

Agovy, Inc.

Lumileds Holding B.v.

Koninklijke Philips Electronics N.v.

Svensson, Carl Patrik Theodor

Lemay, Cynthia

Romano, Linda

Herner, Scott Brad

Linda T Romano

David P Bour

Isik C Kizilyalli

Hui Nie

Richard J Brown

Andrew Paul Edwards

Thomas R Prunty

Chunming Niu

Michael A Kneissl

David P Stumbo

Jian Chen

Xiangfeng Duan

Vijendra Sahi

Jay L Goldman

Stephen A Empedocles

Yaoling Pan

Nathan Fredrick Gardner

J Wallace Parce

David Kirtland Fork

Sungsoo Yi

Shahriar Mostarshed

Christopher L Chua

Robert S Dubrow

Christian G Van De Walle

Lawrence A Bock

James M Hamilton

Madhan M Raj

Decai Sun

Francesco Lemmi

Patrik Svensson

Mahdan Raj

Eric Peeters

Donald Ray Disney

Scott Brad Herner

Noble Marshall Johnson

Thomas L Paoli

Jeng Ping Lu

Werner K Goetz

Donald Leonard Smith

Koenraad F Van Schuylenbergh

Michael Ragan Krames

Ping Mei

Calvin Y H Chow

Francisco A Leon

Mihai A Buretea

John E Northrup

R Hugh Daniels

Patrick Nolan Grillot

George Pontis

David Kalman Biegelsen

Martin F Schubert

Brent Shawhan Krusor

Ying-Lan Chang

Ross D Bringans

Olga Kryliouk

Calvin Y Chow

Daniel Bryce Thompson

Dave P Bour

Carl Patrik Theodor Svensson

Cynthia Lemay

Clarence John Dunnrowicz

Ping Wang

Daniel Hofstetter

Larry Bock

Dave Stumbo

Patrick G Kim

Xianfeng Duan

Parce J Wallace

Erik C Scher

Nicholas K Sheridon

Edward Anthony Richley

Aurelien J F David

Jeffery A Whiteford

Joseph Michael Crowley

Jack A Walker

David Leslie Heald

James C Mikkelsen

G A Connell

Virginia Robbins

Fernando A Ponce

Harold Ackler

Chris G Van De Walle

Patrick N Grillot

Alice Fischer-Colbrie

Chungming Niu

Hugh Daniels

Tanya J Cervantes

Rose M Wood

Don Disney

Michael R Krames

Nathan E Gardner

Donald L Smith

Koenraad F Schuylenbergh

In accordance with embodiments of the invention, at least partial strain relief in a light emitting layer of a III-nitride light emitting device is provided by configuring the surface on which at least one layer of the device grows such that the layer expands laterally and thus at least partially relaxes. This layer is referred to as the strain-relieved layer. In some embodiments, the light emitting layer itself is the strain-relieved layer, meaning that the light emitting layer is grown on a surface that allows the light emitting layer to expand laterally to relieve strain. In some embodiments, a layer grown before the light emitting layer is the strain-relieved layer. In a first group of embodiments, the strain-relieved layer is grown on a textured surface.

Semiconductor light emitting device growing active layer on textured surface

A core-shell nanowire device includes an eave region having a structural discontinuity from the p-plane in the upper tip portion of the shell to the m-plane in the lower portion of the shell. The eave region has at least 5 atomic percent higher indium content than the p-plane and m-plane portions of the shell.

III-nitride nanowire LED with strain modified surface active region and method of making thereof

A light emitting diode (LED) device includes a semiconductor nanowire core, and an In(Al)GaN active region quantum well shell located radially around the semiconductor nanowire core. The active quantum well shell contains indium rich regions having at least 5 atomic percent higher indium content than indium poor regions in the same shell. The active region quantum well shell has a non-uniform surface profile having at least 3 peaks. Each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley, and each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.

A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer.

Coalesced nanowire structures with interstitial voids and method for manufacturing the same

A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

InGaN ohmic source contacts for vertical power devices

A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer has a first dopant concentration. The vertical JFET also includes a III-nitride epitaxial structure coupled to the first III-nitride epitaxial layer. The III-nitride epitaxial structure includes a set of channels of the first conductivity type and having a second dopant concentration, a set of sources of the first conductivity type, having a third dopant concentration greater than the first dopant concentration, and each characterized by a contact surface, and a set of regrown gates interspersed between the set of channels. An upper surface of the set of regrown gates is substantially coplanar with the contact surfaces of the set of sources.

Method and system for planar regrowth in GaN electronic devices

A Schottky diode and method of fabricating the Schottky diode using gallium nitride (GaN) materials is disclosed. The method includes providing an n-type GaN substrate having first and second opposing surfaces. The method also includes forming an ohmic metal contact electrically coupled to the first surface, forming an n-type GaN epitaxial layer coupled to the second surface, and forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer. The AlGaN surface layer has a thickness which is less than a critical thickness, and the critical thickness is determined based on an aluminum mole fraction of the AlGaN surface layer. The method also includes forming a Schottky contact electrically coupled to the n-type AlGaN surface layer, where, during operation, an interface between the n-type GaN epitaxial layer and the n-type AlGaN surface layer is substantially free from a two-dimensional electron gas.

GaN-based Schottky barrier diode with algan surface layer

A method of dicing semiconductor devices includes depositing a continuous first layer over the substrate, such that the first layer imparts a compressive stress to the substrate, and etching grooves in the first layer to increase local stress at the grooves compared to stress at the remainder of the first layer located over the substrate. The method also includes generating a pattern of defects in the substrate with a laser beam, such that a location of the defects in the pattern of defects substantially corresponds to a location of at least some of the grooves in the in the first layer, and applying pressure to the substrate to dice the substrate along the grooves.

Method of stress induced cleaving of semiconductor devices

A method of making an edge terminated semiconductor device includes providing a GaN substrate having a GaN epitaxial layer grown thereon and exposing a portion of the GaN epitaxial layer to ion implantation. The energy dose is selected to provide a resistivity that is at least 90% of maximum achievable resistivity. The method also includes depositing a conductive layer over a portion of the implanted region.

Edge termination by ion implantation in gallium nitride

A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.

Method and system for a GaN vertical JFET utilizing a regrown channel

A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.

Method and system for diffusion and implantation in gallium nitride based devices

A submount for light emitting diode (LED) die includes a substrate containing a plurality of tubs configured to receive an LED die, and a plurality of integrated interconnects integrated into the substrate. At least a portion of the interconnects for each tub have an exposed portion on a side of the submount and at least some of the plurality of the interconnects are not connected to other interconnects in the submount.

LED submount with integrated interconnects

Growing community of inventors

Sunnyvale, CA, United States of America

Linda T Romano