Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Newport Fab, LLC

Liming Tsau

Sam Ziqun Zhao

Henry Chen

Reza Sharifi

Vincent Chen

Surya Battacharya

Akira Ito

Arun Ramakrishnan

Andy Brotman

Sam Komarapalayam Karikalan

Dharmendra Saraswat

Mayank Mayukh

Jay Shiau

Edward Law

Bin Zhao

Guang-Jye Shiau

Neal Andrew Kistler

Jung Wang

Yusang Lin

Robert I Wu

Robert Lutze

Voon Yean Ten

Rong Zeng

Tzu Hsin Huang

Ming Chen

Xiaoming Li

Cheng Lee

Junfei Zhu

Joon Yeob Lee

Ennis T Ogawa

Michael Wang

Yi Liu

Tzu-Hsin Huang

Surya Bhattacharya

A semiconductor package with integrated side wall antennas is provided. An apparatus includes two or more die layers that are bonded together, each of the two or more die layers comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes a first antenna array, the first antenna array comprising a first plurality of antenna array elements formed in at least one of the two or more die layers, wherein the first plurality of antenna array elements is at least partially exposed at the first side wall.

Integrated antennas on side wall of 3D stacked die

A semiconductor product, which comprises a semiconductor chip, an edge integrity detection structure extending along at least part of an edge of the semiconductor chip, and evaluation circuitry formed in and/or on the semiconductor chip, being electrically connected with the edge integrity detection structure, and being configured to evaluate an electric characteristic of the edge integrity detection structure to provide an evaluation signal indicative of a detected edge integrity status of the edge.

Semiconductor product with edge integrity detection structure

Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.

Cantilevered power planes to provide a return current path for high-speed signals

An integrated circuit (IC) package includes a one or more die and an interposer. The interposer is coupled to the die and includes circuit traces. The circuit traces are provided in a serpentine configuration. A method can be used to fabricate an integrated circuit package. The method can use an interposer circuit traces having a configuration that allows the circuit traces to deform under stress, and return to an original state undamaged more readily than a straight conductive trace.

Integrated circuit package with serpentine conductor and method of making

An apparatus includes a substrate that includes one or more routing layers, and an optical module coupled to the substrate. The optical module includes a photonic integrated circuit (PIC) and electronic integrated circuit (EIC), wherein the photonic integrated circuit is at least partially embedded within the substrate. The apparatus further includes a fiber optic coupler coupled to at least one of the substrate or PIC, wherein the PIC is configured to transmit or receive an optical signal via the fiber optic coupler.

Photonics integration in semiconductor packages

An integrated circuit die includes a metal layer, a first passivation layer disposed above the metal layer, an aluminum containing redistribution layer disposed above the first passivation layer, an under bump metallization layer, and a redistribution layer plug. The redistribution layer plug is coupled to the metal layer and disposed in a via in the first passivation layer. The under bump metallization layer is coupled to the aluminum containing redistribution layer above the first passivation layer at a distance from the redistribution layer plug.

Redistribution metal and under bump metal interconnect structures and method

A die edge crack and delamination detection device includes a semiconductor device including an IC active area surrounded by at least one mechanical protection barrier (MPB); one or more metallization layers stacked on the IC active area; a plurality of passive electronic devices placed within the metallization layers at respective predetermined distances from the MPB; and a detection circuit having circuitry. The circuitry is configured to determine a specific metallization layer in which a crack or a delamination is encroaching from an edge of the semiconductor device, determine a lateral distance of a lead end of the crack or the delamination from the MPB, and determine a rate of approach of the crack or the delamination encroaching towards the MPB, via a nominal change in an electrical measurement of at least one of the passive electronic devices.

Die edge crack and delamination detection

Integrated circuits with edge assurance structures are provided for more reliable and efficient monitoring of the die edge integrity using, for example, Automatic (or Automated) Test Equipment (ATE). The edge assurance structures can be used to test, for example, all (100%) of the production materials with virtually no extra cycle time and cost. The edge assurance structure can be located around an edge of the integrated circuit. The edge assurance structure can include a plurality of v-shaped structures that are connected to each other using a plurality of ultra-thick vias. The integrated circuit can include a pad that is coupled to the edge assurance structure. The pad can be used to measure a resistance of the edge assurance structure.

Integrated circuit with die edge assurance structure

According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.

Semiconductor die with fuse window and a monitoring window over a structure which indicates fuse integrity

A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.

Metal-insulator-metal (MIM) capacitor

An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

High-density metal capacitor using dual-damascene copper interconnect

High density metal capacitor using via etch stopping layer as field dielectric in dual-damascence interconnect process

A one-time programming memory element, capable of being manufactured in a 0.13 &#x3bc;m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

System and method for one-time programmed memory through direct-tunneling oxide breakdown

A one-time programming memory element, capable of being manufactured in a 0.13 &#x3bc;m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write circuit, having first and second switches coupled to the capacitor, and a read circuit also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write circuit to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

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Irvine, CA, United States of America

Liming Tsau