International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Marvellworld Trade Ltd.

Lijuan Zhang

Ping-Chuan Wang

Ronald G Filippi

Erdem Kaltalioglu

Timothy Dooling Sullivan

Fen Chen

Mukta G Farooq

Wai-Kin Li

Naftali Eliahu Lustig

John Matthew Safran

Andrew Tae Kim

John A Griesemer

Chandrasekaran Kothandaraman

John Anthony Fitzsimmons

Minhua Lu

Bucknell Chapman Webb

Andrew Herbert Simon

Griselda Bonilla

Thomas M Shaw

Xiao Hu Liu

Junjing Bao

Runzi Chang

Shahab Siddiqui

Samuel S Choi

Long-Ching Wang

Marc Jacobs

Ronen Sinai

An electronic device includes: (i) a first chiplet including a first seal ring, which is disposed in metal layers embedded between a first surface of the first chiplet, and a first substrate of the first chiplet, (ii) a second chiplet including a second seal ring, which is disposed in metal layers embedded between a second surface of the second chiplet, and a second substrate of the second chiplet, and (iii) a third seal ring, which surrounds the first and second chiplets and is disposed in a dielectric substrate extrinsic to the metal layers and overlaying the first and second surfaces of the first and second chiplets.

Double seal ring and electrical connection of multiple chiplets

An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Electromigration monitor

The present disclosure describes a coaxial-interconnect structure that is integrated into a semiconductor component and methods of forming the coaxial-interconnect structure. The coaxial interconnect-structure, which electrically couples circuitry of an integrated-circuit (IC) die to traces of a packaging substrate, comprises a signal core elongated about an axis, a ground shield elongated about the axis, and an insulator disposed between the signal core and the ground shield.

Coaxial-interconnect structure for a semiconductor component

A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) includes at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric.

Embodiments provide a packaging arrangement that includes a high density interconnect bridge for interconnecting dies within the packaging arrangement. The packaging arrangement comprises one or more redistribution layers and an interconnect bridge embedded within the one or more redistribution layers. A first die is coupled to (i) a first portion of the one or more redistribution layers and (ii) a first portion of the interconnect bridge. A second die coupled to a (ii) a second portion of the one or more redistribution layers and (ii) a second portion of the interconnect bridge to electrically couple the first die and the second die via at least the first interconnect bridge.

Packaging arrangements including high density interconnect bridge

A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.

TSV deep trench capacitor and anti-fuse structure

An method including forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion including a plurality of layers of a metallic material and a dielectric material and excluding a semiconductor material, forming a through-substrate via through the BEOL wiring portion and the semiconductor base portion, forming an electronic fuse in the BEOL wiring portion adjacent to the through-substrate via, and forming a guard ring in the BEOL wiring portion surrounding the through-substrate via and the electronic fuse in the BEOL wiring portion, the through-substrate via in the semiconductor base portion being free from the guard ring.

Programmable electrical fuse in keep out zone

A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

Selective local metal cap layer formation for improved electromigration behavior

A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower dielectric layer, a bottom surface of the upper dielectric layer and the top surface of the lower dielectric layer defining an interface; a first wire formed in the lower dielectric layer; a second wire formed in the upper dielectric layer; and wherein a distance between the first wire and the second wire measured in a direction parallel to the interface is below the lithographic resolution limit of the fabrication technology.

Structures and methods for determining TDDB reliability at reduced spacings using the structures

The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Mechanically anchored backside C4 pad

The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC structure according to embodiments of the present invention may include a through-semiconductor via (TSV) embedded within a substrate, the TSV having an axial end; and a metal cap contacting the axial end of the TSV, wherein the metal cap has a greater electrical resistivity than the TSV.

Integrated circuit structure with metal cap and methods of fabrication

The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer; a plurality of vias each embedded within the dielectric layer and coupling the metal layer to the cap of the TSV at respective contact points, wherein the plurality of vias is configured to create a substantially uniform current density throughout the TSV.

Integrated circuit structure with through-semiconductor via

An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region.

Growing community of inventors

Beacon, NY, United States of America

Lijuan Zhang