Applied Materials, Inc.

Lihua Li Huang

Li-Qun Xia

Ellie Y Yieh

Yan Ye

Yunsang Kim

Kang Sub Yim

Gerardo Delgadino

Xiaoye Zhao

Tzu-Fang Huang

Francimar Campana Schmitt

Neungho Shin

Wen H Zhu

Joey Chiu

Fang Tian

A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Method of forming a low-K dual damascene interconnect structure

Low K dielectric films exhibiting low mechanical stress may be formed utilizing various techniques in accordance with the present invention. In one embodiment, carbon-containing silicon oxide films are formed by plasma-assisted chemical vapor deposition at low temperatures (300&#xb0; C. or less). In accordance with another embodiment, as-deposited carbon containing silicon oxide films incorporate a porogen whose subsequent liberation reduces film stress.

Low temperature process to produce low-K dielectrics with low stress by plasma-enhanced chemical vapor deposition (PECVD)

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San Jose, CA, United States of America

Lihua Li Huang