Taiwan Semiconductor Manufacturing Comp. Ltd.

Liang-Yin Chen

Huicheng Chang

Su-Hao Liu

Yee-Chia Yeo

Chia-Cheng Chen

Kuo-Ju Chen

Wei-Ting Chien

Chun-Hung Wu

Ying-Lang Wang

Lun-Kuang Tan

Meng-Han Chou

Li-Ting Wang

Tsan-Chun Wang

Wen-Yen Chen

Chia-Ling Chan

Syun-Ming Jang Jang

Xiong-Fei Yu

Chih-Kai Yang

Jing-Huei Huang

Kei-Wei Chen

Yu-Tien Shen

Wei-Ming You

Huai-Tei Yang

Tang-Kuei Chang

Tsung-Lin Lee

Chang-Miao Liu

Chun-Yen Chang

Ya Hui Chang

Li-Chieh Wu

Hui-Cheng Chang

Kuo-Hsiu Wei

Ting-Kui Chang

Yi-Hsiu Liu

Chia Hsuan Lee

Jie-Huang Huang

Tze-Liang Lee

Yen-Ming Chen

Chih-Hsin Ko

Chih Chieh Yeh

Cheng-Hsien Wu

Ming-Hsi Yeh

Szu-Ying Chen

Chan-Lon Yang

Chun-Hsien Huang

Kai-Hsuan Lee

Kuo-Bin Huang

Jr-Hung Li

Chun-Neng Lin

Tsai-Jung Ho

Pei-Yu Chou

Po-Nan Yeh

Yu-Shih Wang

U-Ting Chiu

Tung-Po Hsieh

Tzu-Yang Ho

Shih-Hsiang Chiu

Meng-Shu Lin

Hong-Chih Liu

Chun-Liang Chen

Ru-Gun Liu

Jyu-Horng Shieh

Yung-Sung Yen

Wei-Liang Lin

Yu-Chang Lin

Yi-Nien Su

Chien-Tai Chan

Chien-I Kuo

Wei-Yip Loh

I-Hsieh Wong

Cheng-Yu Yang

Hung-Hsu Chen

Shu-Huei Suen

Ya-Wen Yeh

Ya-Hui Chang

Kuan-Yu Yeh

Tz-Shian Chen

Cheng-Jung Sung

Chia-Fong Chang

Derek Chen

Hsiang-Ming Chang

Li-Heng Chen

Lin-Yu Huang

Chun-Feng Nieh

Chih-Hung Chen

Wan-Yi Kao

Hui-Chi Huang

Chun-Heng Chen

Sen-Hong Syue

Hong-Mao Lee

Fu-Ming Huang

Chun-Hao Kung

Kao-Feng Liao

Ji Cui

Jhih-Rong Huang

Wei-Wei Liang

Kuan-Kan Hu

Pinyen Lin

Chia-Ling Chung

Yuting Cheng

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Device having an air gap adjacent to a contact plug and covered by a doped dielectric layer

A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device and method for manufacturing the same

A method of forming a semiconductor device includes etching trenches in a substrate to form fin structures, depositing a liner layer to line the trenches, filling the trenches with an insulating layer, performing an ion implantation process to the insulating layer, after performing the ion implantation process, recessing the insulating layer to form shallow trench isolation (STI) regions adjacent the fin structures, and forming a gate crossing the fin structures.

Formation method of shallow trench isolation

In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a position of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Wafer positioning method and apparatus

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Methods of forming semiconductor device

A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

System and method for multiple step directional patterning

A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Method of forming a semiconductor device

In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.

Semiconductor device and method

A method of forming a semiconductor device including performing an ion implantation on a substrate and etching the substrate and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a transistor on a first side of a substrate; performing an ion implantation on a second side of the substrate opposite the first side; after performing the ion implantation, etching the substrate to remove the substrate and form a first recess; and forming a dielectric layer in the first recess.

Semiconductor devices including backside power rails and methods of manufacture

A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

Deposition window enlargement

A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

Semiconductor device and method of manufacture

A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.

Ion exposure method and apparatus

Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Semiconductor devices and methods of manufacture

Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Growing community of inventors

Hsinchu, Taiwan

Liang-Yin Chen