Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Other

Liang-Gi Yao

Shih-Chang Chen

Ming-Fang Wang

Clement Hsingjen Wann

Mong-Song Liang

Chen-Hua Douglas Yu

Jeff J Xu

Yee-Chia Yeo

Yasutoshi Okuno

Chih-Wei Yang

Chi-Chun Chen

Chia-Lin Chen

Tien-Chih Chang

Chenming Hu

Kuen-Chyr Lee

Chien-Hao Chen

Chia-Cheng Chen

Chen-Yi Lee

Chun-Hu Cheng

Ziwei Fang

Fu-Liang Yang

Chao-Hsiung Wang

Weng Chang

Chien-Chao Huang

De-Wei Yu

Ta-Ming Kuan

Yeur-Luen Tu

Pin-Ting Wang

Hua-Tai Lin

Tou-Hung Hou

Tuo-Hung Ho

Chih-Hao Wang

Hun-Jan Tao

Pang-Yen Tsai

Wen-Chin Lee

Chun-Chieh Lin

Erik S Jeng

Yen-Ping Wang

Kuan-Ting Liu

Tuo-Hung Hou

Kun-Yu Lee

Shang-Chih Chen

Hsien-Kuang Chiu

Yue-Feng Chen

Kwong-Jr Tsai

John Chin-Hsiang Lin

Chia Ping Lo

Yeou-Ming Lin

Chih-Chang Chen

Chun Chich Lin

Chung-Ju Lee

Keng-Chu Lin

Huan-Just Lin

Chih-Hao Chang

Ling-Yen Yeh

Shiang-Bau Wang

Cheng-Tung Lin

Ding-Yuan Chen

Chen-Nan Yeh

Chu-Yun Fu

Jaw-Jung Shin

I-Ming Chang

Yu-Rung Hsu

Peng-Fu Hsu

Yusuke Oniki

Kuo-Shu Tseng

Shou Zen Chang

Wei-Ray Lin

Wei-Shan Hu

Tony Liang-Tung Chang

Hsiao-Chin Tuan

Meng-Jaw Cherng

Sen-Huan Huang

Shiang-Peng Cheng

Hung-Yi Luo

Jin Ying

Hung-Chuan Chen

Fu Chin Yang

Chun Chieh Lin

Chia-Ping Lo

Bu-Chin Chung

Mon-Song Liang

Yuh-Min Lin

Shih-Chieh Su

Yue-Feng Cheu

Guei-Chi Guo

Albert Lin

Randy Chang

Stanley Hsu

Ruey-Feng Rau

Kai-Lin Mai

Cc Lin

Shin-Chang Chen

A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.

Method of semiconductor integrated circuit fabrication

A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.

A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.

A method of cleaning a semiconductor structure includes rotating a semiconductor structure. The method of cleaning further includes cleaning the semiconductor structure with a hydrogen fluoride (HF)-containing gas. A method of forming a semiconductor device includes forming a recess in a source/drain (S/D) region of a transistor. The method of forming further includes cleaning the recess with a HF-containing gas, the HF-containing gas having an oxide removing rate of about 2 nanometer/minute (nm/min) or less. The method of forming further includes epitaxially forming a strain structure in the recess after the cleaning the recess, the strain structure providing a strain to a channel region of the transistor.

Method of forming a semiconductor structure

A method of fabricating a semiconductor device includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer.

Methods of forming gate dielectric material

A semiconductor device includes a substrate and a gate structure over the substrate. The gate structure includes a dielectric portion and an electrode portion that is disposed over the dielectric portion. The dielectric portion includes a carbon-doped high dielectric constant (high-k) dielectric layer over the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion.

Semiconductor device having high-K gate dielectric layer

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium SiGeand x is less than about 30%.

Structure and method for integrated devices on different substartes with interfacial engineering

A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.

Method of scavenging impurities in forming a gate stack having an interfacial layer

A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.

Semiconductor structure having interfacial layer and high-k dielectric layer

A method includes performing a first probing on a sample integrated circuit structure to generate a first Raman spectrum. During the first probing, a first laser beam having a first wavelength is projected on the sample integrated circuit structure. The method further includes performing a second probing on the sample integrated circuit structure to generate a second Raman spectrum, wherein a Tip-Enhanced Raman Scattering (TERS) method is used to probe the sample integrated circuit structure. During the second probing, a second laser beam having a second wavelength different from the first wavelength is projected on the sample integrated circuit structure. A stress in a first probed region of the sample integrated circuit structure is then from the first Raman spectrum and the second Raman spectrum.

Stress analysis of 3-D structures using tip-enhanced Raman scattering technology

A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.

Method of forming semiconductor structure

A method of performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the method includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 700&#xb0; C. Another method of performing an annealing process on an interfacial layer over a semiconductor substrate, the second method includes supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas. The method further includes heating the interfacial layer at a temperature less than or equal to 600&#xb0; C.

Method for reducing interfacial layer thickness for high-k and metal gate stack

The disclosure relates to integrated circuit fabrication and, more particularly, to a semiconductor device with a high-k gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate and a gate structure disposed over the substrate. The gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion, and the dielectric portion comprises a carbon-doped high-k dielectric layer on the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion.

Method of fabricating a carbon-free dielectric layer over a carbon-doped dielectric layer

A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

Process to make high-K transistor dielectrics

Multi-layer scavenging metal gate stack for ultra-thin interfacial dielectric layer

Growing community of inventors

Hsinchu, Taiwan

Liang-Gi Yao