Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Liang Choo Hsia

Mei Sheng Zhou

Fan Zhang

John Leonard Sudijono

Alex K H See

Chung Woh Lai

Bei Chao Zhang

Tae Jong Lee

Dong Kyun Sohn

Jinping Liu

Huang Liu

Hui Peng Koh

Alex See

Wei Lu

Hai Cong

Xiaomei Bu

Khee Yong Lim

Yong Meng Lee

Wenhe Lin

Young Way Teh

Wuping Liu

Wee Leng Tan

Jin Ping Liu

Chim Seng Seet

Johnny Widodo

Chew Hoe Ang

Juan Boon Tan

James Yong Meng Lee

Kheng Chok Tee

Zhao Lun

Shailendra Mishra

Victor Seng Keong Lim

Yong Kong Siew

Tong Qing Chen

Wen Zhi Gao

Kho Liep Chok

Fang Hong Gn

Jane Hui

Jia Zhen Zheng

Benjamin Colombeau

Sanford Chu

Yung Fu Chong

Soh Yun Siah

Yeow Kheng Lim

Shiang Yang Ong

Sia Kim Tan

Francis Lionel Benistant

Soon Yoeng Tan

Sung Mun Jung

Yun Ling Tan

Chun Hui Low

Fang Chen

Meisheng Zhou

Qun Ying Lin

Huey Ming Chong

Swee Tuck Woo

Raymond Joy

Bo Tao

Timothy Phua

Rachel Yie Fang Wai

Boon Meng Seah

Yew Tuck Chow

Yong Chiang Ee

Jeff Jianhui Ye

Debora Chyiu Hyia Poon

Binbin Zhou

Simon Yew-Meng Chooi

Yelehanka Ramachandramurthy Pradeep

Jae Gon Lee

Kin Leong Pey

Eng Hua Lim

Lup San Leong

Zheng Zou

Jeffrey C Lam

Liu Huang

Zhihong Mai

David Vigar

Fei Xu

Beichao Zhang

Luona Goh

Pik Kee Tan

Yee Mei Foong

Hwa Weng Koh

Wenzhan Zhou

Xian Bin Wang

Lydia Wong

Bin Yang

Chian Yuh Sin

Hao Zhang

San Leong Liew

Jianhui Ye

Shao Beng Law

Cheng-Cheh Tan

Ben Ong

Zhengquan Zhang

K H Alex See

Jyoti Gupta

Hung Chang Yu

Hury Ming Chong

Chew-Hue Ang

A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

Slot designs in wide metal lines

A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.

Reliable interconnect for semiconductor device

A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction

A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

Strained channel transistor structure and method

A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

Method for fabricating a semiconductor device having an epitaxial channel and transistor having same

A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness T. A capping layer is formed on the substrate having a formed thickness T. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness T. The thickness of the capping layer is adjusted from Tto about a target thickness T.

Dielectric stack

A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Spacer-less low-K dielectric processes

An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct errors in the input mask pattern.

Statistical optical proximity correction

A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.

Integrated circuit and method of fabrication thereof

According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

Method and system for introducing physical damage into an integrated circuit device for verifying testing program and its results

A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

Method of forming high-k dielectric stop layer for contact hole opening

A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect.

Defect monitoring in semiconductor device fabrication

Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.

Critical dimension for trench and vias

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Singapore, Singapore

Liang Choo Hsia