No. 24 Research Institute of China Electronics Technology Group Corporation

China Electronic Technology Corporation, 24th Research Institute

Liang Chen

Tao Liu

Yan Wang

Guang-Bing Chen

Hequan Jiang

Dong-Bing Fu

Yu-Xin Wang

Kaizhou Tan

Yonghui Yang

Peijian Zhang

Sheng Qiu

Tian Xiao

Jiahao Zhang

Yang Pu

Ying Pei

Pengfei Wang

Guangbo Li

Wei Cui

Yu-Jun Yang

Xiaoquan Li

The MOS device with resistive field plate for realizing conductance modulation field effect in the present invention is based on the existing trench gate MOS device, and a semi-insulating resistive field plate electrically connected to the trench gate structure and the drain structure is added in the drift region, where the trench gate structure can control the on-off of the MOS channel, and the semi-insulating resistive field plate can adjust the doping concentration of the drift region to modulate the conductance of the on-state drift region and the distribution of off-state high-voltage blocking electric field, thus a lower on-resistance can be obtained. In addition, the modern 2.5-dimensional processing technology based on deep trench etching is adopted in the present invention, which is conducive to the miniaturization design and high density design of the structure and is more suitable for the More than Moore (beyond Moore) development of modern integrated semiconductor devices.

MOS device with resistive field plate for realizing conductance modulation field effect and preparation method thereof

The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Chip ESD protection circuit

Growing community of inventors

Chongqing, China

Liang Chen