United Microelectronics Corp.

Liang-An Huang

Chin-Fu Lin

Chih-Chung Wang

Wen-Fang Lee

Sheng-Chen Chung

Chiu-Te Lee

Ke-Feng Lin

Nien-Chung Li

Ching-Chung Yang

Kuang-Hsiu Chen

Chun-Hung Cheng

Chin-Chia Kuo

Yau-Kae Sheu

Ming-Hua Tsai

Chen-An Kuo

Yu-Chieh Lin

Jung Han

Chun-Lin Chen

Yu-Chun Huang

Yuan-Cheng Yang

Hsin-Liang Liu

Hsiang-Hua Hsu

Yan-Huei Li

Kai-Ting Hu

Yu-Ciao Lin

An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.

EDMOS and fabricating method of the same

A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.

Metal-oxide-semiconductor transistor and method of fabricating the same

A method of manufacturing shallow trench isolations is provided in the present invention, which includes the steps of providing a substrate, performing a zero etch to form preliminary trenches in the substrate, performing a STI etch to the preliminary trenches to form final trenches, where the final trenches are deeper and steeper than the preliminary trenches, and filling up the final trenches with insulating material to form shallow trench isolations.

Shallow trench isolations and method of manufacturing the same

A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Fabricating method of shallow trench isolation structure

Growing community of inventors

Tainan, Taiwan

Liang-An Huang