United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Li-Wei Feng

Jyh-Shyang Jenq

Shih-Hung Tsai

Chien-Ting Ho

Ying-Chiao Wang

Chao-Hung Lin

Yu-Cheng Tung

Shih-Fang Hong

Tsung-Ying Tsai

Ssu-I Fu

Shih-Fang Tzou

Yu-Hsiang Hung

Hon-Huei Liu

Chih-Kai Hsu

Yu-Chieh Lin

Chien-Ting Lin

Janbo Zhang

Yi-Wei Chen

Tong-Jyun Huang

Kai-Ping Chen

Ming-Te Wei

Chien-Cheng Tsai

Kuei-Hsuan Yu

Jia-Rong Wu

Yu-Shu Lin

YI-Fan Li

Nan-Yuan Huang

Wen-Chieh Lu

Tzu-Tsen Liu

Chih-Sen Huang

Chia-Lung Chang

Tien-Chen Chan

Shih-Han Hung

Yu-Ching Chen

Hui-Ling Chuang

Fu-Che Lee

Ching-Wen Hung

Chun-Yuan Wu

Chi-Mao Hsu

Yi-Hui Lee

Tsun-Min Cheng

Hsin-Fu Huang

Pin-Hong Chen

Ying-Cheng Liu

Chih-Chieh Tsai

Chiu-Hsien Yeh

Wei-Hsin Liu

Tzu-Chieh Chen

Yi-An Huang

Chia-Wei Wu

Kai-Jiun Chang

Po-Chun Chen

Ger-Pin Lin

Chia-Chen Wu

Tzu-Chin Wu

Jui-Min Lee

Po-Han Wu

Yi-Kuan Wu

Kun-Hsin Chen

Chung-Yen Feng

Li-Wei Liu

Chih-Chi Cheng

Enping Cheng

Ching-Yu Chang

En-Chiuan Liou

Tri-Rung Yew

Chen-Ming Huang

Hsin-Yu Chen

An-Chi Liu

Neng-Hui Yang

Shu-Yen Chan

Shou-Wei Hsieh

Hung-Chan Lin

Ching-Ling Lin

Yi-Wen Chen

Chun-Hao Lin

Ming-Hua Chang

Chun-Jen Chen

Chun-Yao Yang

Li-Chiang Chen

Chia-Hsun Tseng

Li-Chieh Hsu

I-Cheng Hu

Feng-Ming Huang

Tien-I Wu

Ming-Shiou Hsieh

Rong-Sin Lin

Chih-Wei Wu

Yi-Ren Chen

Mei-Chen Chen

Emily Sh Huang

Bo-Ruei Cheng

The invention discloses a semiconductor memory device, which is characterized by comprising a substrate defining a cell region and an adjacent periphery region, a plurality of bit lines are arranged on the substrate and arranged along a first direction, each bit line comprises a conductive part, and the bit line comprises four sidewalls, and a spacer surrounds the four sidewalls of the bit line, the spacer comprises two short spacers covering two ends of the conductive part, two long spacers covering the two long sides of the conductive part, and a plurality of storage node contact isolations located between any two adjacent bit lines, at least a part of the storage node contact isolations cover directly above the spacers. The structure of the invention can improve the electrical isolation effect, preferably avoid leakage current and improve the quality of components.

Semiconductor memory device

The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Storage node contact structure of a memory device

A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Semiconductor structure with capacitor landing pad and method of making the same

The present disclosure relates to a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Semiconductor device having bit line comprising a plurality of pins extending toward the substrate

The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width Xand a width X. The width Xis aligned with the top portion of the rounding hard mask in a horizontal direction, and the width Xis aligned with the bottom portion of the rounding hard mask in the horizontal direction, Xis greater than or equal to X

Semiconductor device and manufacturing method thereof

The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Method of fabricating semiconductor memory having a second active region disposed at an outer side of a first active region

The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, the stacked structure comprises a first support layer, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, a portion of a sidewall of the first support layer directly contacts a portion of a sidewall of the second support layer, and a capacitor structure located in the cell array region.

Manufacturing method of semiconductor device and semiconductor device

The present disclosure relates to a fabricating method of a semiconductor memory device including the following steps. Firstly, a substrate is provided, and a plurality of gate structures is formed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. Next, a plurality of isolation fins is formed on the substrate, wherein each of the isolation fins is parallel with each other and extends along the first direction, over each of the gate structures respectively. After forming the isolation fins, at least one bit line is formed on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Method of forming semiconductor memory device comprises a bit line having a plurality of pins extending along a direction being perpendicular to a substrate

A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.

Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate

Semiconductor memory device having a second active region disposed at an outer side of a first active region

A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.

Semiconductor device

The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, and a capacitor structure located in the cell array region.

A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a first oxide layer in the trench; forming a silicon layer on the first oxide layer; performing an oxidation process to transform the silicon layer into a second oxide layer; and planarizing the second oxide layer and the first oxide layer to form a shallow trench isolation (STI).

Method for fabricating semiconductor device

A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

Semiconductor structure and fabrication method thereof

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Kaohsiung, Taiwan

Li-Wei Feng